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Re: PATCH: fine-tuning for can_store_by_pieces
Nigel Stephens <nigel@mips.com> writes:
> Richard Sandiford wrote:
>> Sandra Loosemore <sandra@codesourcery.com> writes:
>>
>>> OK, but what I was really asking was, is there a way to *test* for
>>> situations where we should generate the lui/ori/sw sequences instead
>>> of the lw/sw? Some combination of TARGET_foo flags and/or the size of
>>> the string?
>>>
>>
>> Well, I suppose:
>>
>> !optimize_size && !TARGET_MIPS16 && mips_issue_rate () > 1
>
> Many MIPS dual-issue processors are asymettric, and may be able to issue
> lui, ori and sw down only one pipe or the other -- not both in parallel.
> So I don't think that testing mips_issue_rate() is sufficient.
True. I suppose I'm biased because all the processors whose schedulers
I've worked on could issue stores down one pipe and arithmetic
instructions down the other.
I assume you think we should stick the uncoditional zero here?
Richard