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Hi, The problem here is that with IV-OPTs (and other passes like PRE) creating temporary decls and those decls have artifical set on them. This causes us not to mark the RTL reg with REG_POINTER so we get a "random" order for the load with index instruction under PowerPC. This matters more for Power 6 than it does any where else. Since the original reason why we decided not to mark them REG_POINTER (http://gcc.gnu.org/ml/gcc-patches/2004-06/msg00020.html) was because we would get the incorrect answer for pa-hppux has been removed with pointer plus, we can revert the patch which Jeff did to fix this. This patch alone gives a 40% improvement on facerec. This also changes cfgexpand.c which contains the same code now (this was added after Jeff's patch went in). I would like someone (John?) bootstrap and test this on hppa-hpux for me? OK? Bootstrapped and tested on both i386-apple-darwin and powerpc64-linux-gnu with no regressions. Thanks, Andrew Pinski ChangeLog: * cfgexpand.c (expand_one_register_var): Mark pointer DECL_ARTIFICIAL as REG_POINTER also. * stmt.c (expand_decl): Likewise.
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