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Re: Re: [Patch] New: CR16 port
- From: Rask Ingemann Lambertsen <rask at sygehus dot dk>
- To: Pompapathi V Gadad <pompapathi at gmail dot com>
- Cc: "Gadad, Pompapathi V" <Pompapathi dot V dot Gadad at nsc dot com>, gcc-patches at gcc dot gnu dot org
- Date: Fri, 13 Jul 2007 16:44:26 +0200
- Subject: Re: Re: [Patch] New: CR16 port
- References: <20070711233258.GX5690@sygehus.dk> <4697387B.20908@gmail.com>
On Fri, Jul 13, 2007 at 02:01:55PM +0530, Pompapathi V Gadad wrote:
> Rask Ingemann Lambertsen wrote:
> >>+(define_insn "mov<mode>_regs"
[4 mov patterns in total]
> >
> >These would normally be one pattern with five alternatives. A reg->reg
> >copy can turn into a reg->mem copy during reload, for example.
> >
> Well, I started with suggestion you had: Having 5 alternatives in a single pattern.
> It turns out that some of the pattern generated pass through predicate test but won't find
> an appropriate alternative. For example, in CR16 ISA, immediate memory store instruction
> does not have 32-bit store operation variant. Therefore, I had to break up the single pattern into
> multiple patterns. The store immediate pattern have "SHORT" (stands for QI and HI) macro
> expansion while others have ALLMT (stands for QI, HI, SI, SF)
You could define "LONG" to expand to SI and SF and use something like
this:
(define_insn "*mov<mode>"
[(set (match_operand:LONG 0 "nonimmediate_operand" "=r, r, r,m")
(match_operand:LONG 1 "general_operand" "r,<iF>,m,r"))]
"register_operand (operands[0], <MODE>mode)
|| register_operand (operands[1], <MODE>mode)"
"@
mov<tIsa>\t%1, %0
mov<tIsa>\t%1, %0
load<tIsa>\t%1, %0
stor<tIsa>\t%1, %0"
[(set_attr "length" "2,<lImmArith>,<lImmArith>,<lImmArith>")]
)
(define_insn "*mov<mode>"
[(set (match_operand:SHORT 0 "nonimmediate_operand" "=r, r, r,m, m")
(match_operand:SHORT 1 "general_operand" "r,<iF>,m,r,<LL>"))]
"!store_operand (operands[0], <MODE>mode)
|| register_operand (operands[1], <MODE>mode)
|| u4bits_operand (operands[1], <MODE>mode)"
"@
mov<tIsa>\t%1, %0
mov<tIsa>\t%1, %0
load<tIsa>\t%1, %0
stor<tIsa>\t%1, %0
stor<tIsaShort>\t%1, %0"
[(set_attr "length" "2,<lImmArith>,<lImmArith>,<lImmArith>,<lImmShort>")]
)
You may have to adjust the predicates a little.
--
Rask Ingemann Lambertsen