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Re: ARM: enable interpreter, add locks code


Andrew Haley wrote:

+/* Atomic compare and exchange.  These sequences are not actually
+   atomic; there is a race if *ADDR != OLD_VAL and we are preempted
+   between the two swaps.  However, they are very close to atomic, and
+   are the best that a pre-ARMv6 implementation can do without
+   operating system support.  LinuxThreads has been using these
+   sequences for many years.  */

Wow! That is terrible.


Is there some way to do proper synchronization if the target CPU supports it?

David Daney


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