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PATCH: FAIL: gcc.target/i386/sse2-vec-5.c on gcc-4.2 branch
- From: "H. J. Lu" <hjl at lucon dot org>
- To: Uros Bizjak <ubizjak at gmail dot com>
- Cc: gcc-patches at gcc dot gnu dot org
- Date: Thu, 21 Jun 2007 06:45:33 -0700
- Subject: PATCH: FAIL: gcc.target/i386/sse2-vec-5.c on gcc-4.2 branch
- References: <5787cf470706210114p76f8ace1q228ae075be1ae6d1@mail.gmail.com> <20070621131559.GA12910@lucon.org> <5787cf470706210624p64b91bf1gf3234286e80a4b52@mail.gmail.com>
On Thu, Jun 21, 2007 at 03:24:56PM +0200, Uros Bizjak wrote:
> On 6/21/07, H. J. Lu <hjl@lucon.org> wrote:
>
> >> Also, the definition of __builtin_ia32_vec_ext_v16qi in the mainline
> >> should be enabled only for OPTION_MASK_ISA_SSE4_1, as current
> >> definition is also enabled for SSE2:
> >>
> >> def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi",
> >> ftype, IX86_BUILTIN_VEC_EXT_V16QI);
> >>
> >> I propose that sse2-vec-5.c is removed from the testsuite in gcc-4_2
> >> branch and mainline.
> >
> >__builtin_ia32_vec_ext_v16qi, like many other vector extra builtins,
> >is supported by SSE2, but not with single instruction. I don't think
> >it should be removed from mainline.
>
> I hardly see the point of having builtin for non-existing insn, but if
> this is the case, we should add missing definition to gcc-4.2 (it is a
> three-liner patch).
>
> >I will remove sse2-vec-5.c from 4.2 since __builtin_ia32_vec_ext_v16qi
> >isn't available there.
>
> No, a better solution is to add missing builtin definition to gcc-4.2.
I already removed it from gcc 4.2. Here is a patch to add it back.
I am testing it on Linux/x86-64 now.
H.J.
----
2007-06-21 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/i386.c (ix86_builtins): Add IX86_BUILTIN_VEC_EXT_V16QI.
(ix86_init_mmx_sse_builtins): Add __builtin_ia32_vec_ext_v16qi.
(ix86_expand_builtin): Handle IX86_BUILTIN_VEC_EXT_V16QI.
--- gcc/config/i386/i386.c.sse2 2007-06-21 06:31:23.000000000 -0700
+++ gcc/config/i386/i386.c 2007-06-21 06:39:42.000000000 -0700
@@ -14646,6 +14646,7 @@ enum ix86_builtins
IX86_BUILTIN_VEC_EXT_V4SF,
IX86_BUILTIN_VEC_EXT_V4SI,
IX86_BUILTIN_VEC_EXT_V8HI,
+ IX86_BUILTIN_VEC_EXT_V16QI,
IX86_BUILTIN_VEC_EXT_V2SI,
IX86_BUILTIN_VEC_EXT_V4HI,
IX86_BUILTIN_VEC_SET_V8HI,
@@ -15749,6 +15750,10 @@ ix86_init_mmx_sse_builtins (void)
def_builtin (MASK_MMX, "__builtin_ia32_vec_ext_v2si",
ftype, IX86_BUILTIN_VEC_EXT_V2SI);
+ ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
+ integer_type_node, NULL_TREE);
+ def_builtin (MASK_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
+
/* Access to the vec_set patterns. */
ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
intHI_type_node,
@@ -16711,6 +16716,7 @@ ix86_expand_builtin (tree exp, rtx targe
case IX86_BUILTIN_VEC_EXT_V4SF:
case IX86_BUILTIN_VEC_EXT_V4SI:
case IX86_BUILTIN_VEC_EXT_V8HI:
+ case IX86_BUILTIN_VEC_EXT_V16QI:
case IX86_BUILTIN_VEC_EXT_V2SI:
case IX86_BUILTIN_VEC_EXT_V4HI:
return ix86_expand_vec_ext_builtin (arglist, target);
--- gcc/testsuite/gcc.target/i386/sse2-vec-5.c.sse2 2007-06-21 06:32:41.000000000 -0700
+++ gcc/testsuite/gcc.target/i386/sse2-vec-5.c 2007-06-21 06:32:26.000000000 -0700
@@ -0,0 +1,49 @@
+/* { dg-do run { target i?86-*-* x86_64-*-* } } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+
+static void
+sse2_test (void)
+{
+ union
+ {
+ __m128i x;
+ char c[16];
+ short s[8];
+ int i[4];
+ long long ll[2];
+ } val1;
+ char res[16];
+ int masks[16];
+ int i;
+
+ for (i = 0; i < 16; i++)
+ val1.c[i] = i;
+
+ res[0] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 0);
+ res[1] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 1);
+ res[2] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 2);
+ res[3] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 3);
+ res[4] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 4);
+ res[5] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 5);
+ res[6] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 6);
+ res[7] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 7);
+ res[8] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 8);
+ res[9] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 9);
+ res[10] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 10);
+ res[11] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 11);
+ res[12] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 12);
+ res[13] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 13);
+ res[14] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 14);
+ res[15] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 15);
+
+ for (i = 0; i < 16; i++)
+ masks[i] = i;
+
+ for (i = 0; i < 16; i++)
+ if (res[i] != val1.c [masks[i]])
+ abort ();
+}