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Re: PATCH: Ensure 8 byte alignment if > 8 byte alignment is preferred

On 6/21/07, H. J. Lu <hjl@lucon.org> wrote:

> I think we should use ".p2align 4,,10" instead of ".p2align 4,,7"
> for 64bit. It will optimize for more cases for 64bit.
>

Here is a patch to do that. 

Can you show the impact of this patch in an example? Does this fix a
runtime regression in PR31897 (Comment #1 shows the regression on when
run in 32bit mode on

processor       : 0
vendor_id       : GenuineIntel
cpu family      : 15
model           : 4
model name      : Intel(R) Xeon(TM) CPU 3.60GHz
stepping        : 10


2007-06-20 H.J. Lu <hongjiu.lu@intel.com>

        * config/i386/i386.c (processor_target_table): Increase maximum
        skip from 7 byte to 10 byte for Pentium Pro, Core 2 Duo and
        default 64bit.

        * config/i386/linux.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Ensure 8
        byte alignment if > 8 byte alignment is preferred.
        * config/i386/x86-64.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Likewise.

This is OK for mainline.

Uros.

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