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[PATCH m32c] PR target/32335 ICE in cselib_record_set, at cselib.c:1508
- From: Rask Ingemann Lambertsen <rask at sygehus dot dk>
- To: gcc-patches at gcc dot gnu dot org
- Cc: dj at redhat dot com
- Date: Mon, 18 Jun 2007 14:37:50 +0200
- Subject: [PATCH m32c] PR target/32335 ICE in cselib_record_set, at cselib.c:1508
The problem here is that the m32c prologue and epilogue has insns which
modify the same register multiple times inside a parallel. After the dataflow
merge, cselib rejects such insns, and IMHO, they are invalid. The patch
below fixes it and the ICE goes away.
The patch is still not enough to make the m32c build again, as it gets a
little further in building libgcc, only to fail with this:
/home/rask/build/gcc-m32c-unknown-elf/./gcc/xgcc [...] -c /n/08/rask/src/gcc/libgcc/../gcc/unwind-dw2.c
/n/08/rask/src/gcc/libgcc/../gcc/unwind.inc: In function '_Unwind_Resume':
/n/08/rask/src/gcc/libgcc/../gcc/unwind.inc:241: internal compiler error: in global_alloc, at global.c:514
I'll let someone else take over from here.
:ADDPATCH m32c:
2007-06-18 Rask Ingemann Lambertsen <rask@sygehus.dk>
PR target/32335
* config/m32c/m32c.c: Include dataflow header file.
(m32c_emit_prologue): Adjust for prologue insn change.
* config/m32c/prologue.md (prologue_enter_16): Only modify SP_REGNO
once inside a PARALLEL. Assume frame size passed in operand 0
includes space to save the fb register.
(prologue_enter_24): Likewise.
(epilogue_exitd): Only modify SP_REGNO once inside a PARALLEL.
Index: config/m32c/m32c.c
===================================================================
--- config/m32c/m32c.c (revision 125635)
+++ config/m32c/m32c.c (working copy)
@@ -49,6 +49,7 @@
#include "tm_p.h"
#include "langhooks.h"
#include "tree-gimple.h"
+#include "df.h"
/* Prototypes */
@@ -3977,8 +3978,8 @@ m32c_emit_prologue (void)
if (cfun->machine->use_rts == 0)
F (emit_insn (m32c_all_frame_related
(TARGET_A16
- ? gen_prologue_enter_16 (GEN_INT (frame_size))
- : gen_prologue_enter_24 (GEN_INT (frame_size)))));
+ ? gen_prologue_enter_16 (GEN_INT (frame_size + 2))
+ : gen_prologue_enter_24 (GEN_INT (frame_size + 4)))));
if (extra_frame_size)
{
Index: config/m32c/prologue.md
===================================================================
--- config/m32c/prologue.md (revision 125635)
+++ config/m32c/prologue.md (working copy)
@@ -33,7 +33,7 @@
; We assume dwarf2out will process each set in sequence.
(define_insn "prologue_enter_16"
- [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNO)))
+ [(set (mem:HI (plus:HI (reg:HI SP_REGNO) (const_int -2)))
(reg:HI FB_REGNO))
(set (reg:HI FB_REGNO)
(reg:HI SP_REGNO))
@@ -42,12 +42,17 @@
(match_operand 0 "const_int_operand" "i")))
]
"TARGET_A16"
- "enter\t%0"
+ {
+ /* This is due to binutils bug gas/4629. */
+ if (INTVAL (operands[0]) == 2)
+ return "enter\t#0";
+ return "enter\t%0-2";
+ }
[(set_attr "flags" "x")]
)
(define_insn "prologue_enter_24"
- [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
+ [(set (mem:SI (plus:PSI (reg:PSI SP_REGNO) (const_int -4)))
(reg:SI FB_REGNO))
(set (reg:PSI FB_REGNO)
(reg:PSI SP_REGNO))
@@ -56,7 +61,12 @@
(match_operand 0 "const_int_operand" "i")))
]
"TARGET_A24"
- "enter\t%0"
+ {
+ /* This is due to binutils bug gas/4659. */
+ if (INTVAL (operands[0]) == 4)
+ return "enter\t#0";
+ return "enter\t%0-4";
+ }
[(set_attr "flags" "x")]
)
@@ -94,12 +104,10 @@
(define_insn "epilogue_exitd"
[(set (reg:PSI SP_REGNO)
- (reg:PSI FB_REGNO))
- (set (reg:PSI FB_REGNO)
- (mem:PSI (reg:PSI SP_REGNO)))
- (set (reg:PSI SP_REGNO)
- (plus:PSI (reg:PSI SP_REGNO)
+ (plus:PSI (reg:PSI FB_REGNO)
(match_operand 0 "const_int_operand" "i")))
+ (set (reg:PSI FB_REGNO)
+ (mem:PSI (reg:PSI FB_REGNO)))
(return)
]
""
--
Rask Ingemann Lambertsen