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Re: PATCH: enable odd floating-point registers for MIPS32 and MIPS64

From: Sandra Loosemore <sandra at codesourcery dot com>
To: Eric Christopher <echristo at apple dot com>
Cc: GCC Patches <gcc-patches at gcc dot gnu dot org>
Date: Tue, 08 May 2007 08:59:54 -0400
Subject: Re: PATCH: enable odd floating-point registers for MIPS32 and MIPS64
References: <463F8B8B.8040600@codesourcery.com> <67590672-EC78-4498-A71F-6CF53EDEAB8E@apple.com>

Eric Christopher wrote:

On May 7, 2007, at 1:26 PM, Sandra Loosemore wrote:

2007-05-07  Sandra Loosemore  <sandra@codesourcery.com>
            Nigel Stephens  <nigel@mips.com>

    gcc/
    * config/mips/mips.h (MAX_FPRS_PER_FMT): Renamed from FP_INC.
    Update comments and all uses.
    (MIN_FPRS_PER_FMT): Define.
    * config/mips/mips.c (function_arg): Fix to correctly handle
    the -mips32r2 -mfp64 -mabi=32 case.
    (override_options): Enable use of odd-numbered registers for
    SFmode values on MIPS32.
    (mips_save_reg_p): Save whole floating-point register pair if
    either half is used.
    (compute_frame_size): Fix comment.

OK.

Thanks. I've just committed the patch.

-Sandra

References:
- PATCH: enable odd floating-point registers for MIPS32 and MIPS64
  - From: Sandra Loosemore
- Re: PATCH: enable odd floating-point registers for MIPS32 and MIPS64
  - From: Eric Christopher

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