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Re: [PING] [m32c] mul and div insn
- From: DJ Delorie <dj at redhat dot com>
- To: naveen dot hs at kpitcummins dot com
- Cc: gcc-patches at gcc dot gnu dot org
- Date: Tue, 24 Apr 2007 14:53:34 -0400
- Subject: Re: [PING] [m32c] mul and div insn
- References: <B9D27836A814694B95A1C294F714576688D2BE@sohm.kpit.com>
> Please consider this as the formal reminder for applying the patch
> which was posted at the following link as you had suggested.
> http://gcc.gnu.org/ml/gcc-patches/2006-07/msg00570.html
Immediate operands are always VOIDmode. Why did you add modes to
those operands?
HL_REGS is not the right class for r2r0 and r3r1. Use R03 for that
(it even says that in m32c.h, near REG_CLASS_CONTENTS). Register
classes must include ALL the registers used for concatentated
registers, not just the first register of each concatenated register.
Divide cannot use different registers for operands 0 and 1. You must
use a matching constraint for operand 1.
Do you really need the sign/zero extends for the divide? Doesn't GCC
do the promotions according to the language standards before emitting
the divide?