This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
PATCH: Correct SSE instruction lengths
- From: "H. J. Lu" <hjl at lucon dot org>
- To: gcc-patches at gcc dot gnu dot org
- Date: Sat, 21 Apr 2007 14:30:39 -0700
- Subject: PATCH: Correct SSE instruction lengths
This patch corrects some SSE instruction lengths. It also adds a
new attribute, prefix_extra, for additional byte in SSSE3/SSE4
instructions. It defaults to 0.
H.J.
----
2007-04-21 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/i386.md (prefix_extra): New attribute.
(length): Add prefix_extra.
* onfig/i386/sse.md (sse2_movdqu): Set prefix_data16.
(sse2_movntv2di): Likewise.
(sse2_cvtps2dq): Likewise.
(sse2_cvtpd2pi): Likewise.
(sse2_cvttpd2pi): Likewise.
(*sse2_cvtpd2ps): Likewise.
(*add<mode>3): Likewise.
(sse2_ssadd<mode>3): Likewise.
(sse2_usadd<mode>3): Likewise.
(*sub<mode>3): Likewise.
(sse2_sssub<mode>3): Likewise.
(sse2_ussub<mode>3): Likewise.
(*mulv8hi3): Likewise.
(*smulv8hi3_highpart): Likewise.
(*umulv8hi3_highpart): Likewise.
(sse2_umulv2siv2di3): Likewise.
(sse2_pmaddwd): Likewise.
(ashr<mode>3): Likewise.
(lshr<mode>3): Likewise.
(ashl<mode>3): Likewise.
(sse2_ashlti3): Likewise.
(sse2_lshrti3): Likewise.
(*umaxv16qi3): Likewise.
(*smaxv8hi3): Likewise.
(*uminv16qi3): Likewise.
(*sminv8hi3): Likewise.
(sse2_eq<mode>3): Likewise.
(sse2_gt<mode>3): Likewise.
(*and<mode>3): Likewise.
(sse2_nand<mode>3): Likewise.
(*ior<mode>3): Likewise.
(*xor<mode>3): Likewise.
(sse2_packsswb): Likewise.
(sse2_packssdw): Likewise.
(sse2_packuswb): Likewise.
(sse2_punpckhbw): Likewise.
(sse2_punpcklbw): Likewise.
(sse2_punpckhwd): Likewise.
(sse2_punpcklwd): Likewise.
(sse2_punpckhdq): Likewise.
(sse2_punpckldq): Likewise.
(sse2_punpckhqdq): Likewise.
(sse2_punpcklqdq): Likewise.
(*sse2_pinsrw): Likewise.
(*sse2_pextrw): Likewise.
(sse2_pshufd_1): Likewise.
(sse2_uavgv16qi3): Likewise.
(sse2_uavgv8hi3): Likewise.
(sse2_psadbw): Likewise.
(sse2_pmovmskb): Likewise.
(*sse2_maskmovdqu): Likewise.
(*sse2_maskmovdqu_rex64): Likewise.
(sse4a_extrqi): Likewise.
(sse4a_extrq): Likewise.
(sse3_lddqu): Set prefix_rep.
(sse3_addsubv4sf3): Likewise.
(sse3_haddv4sf3): Likewise.
(sse3_hsubv4sf3): Likewise.
(sse_cvtss2si): Likewise.
(sse_cvtss2si_2): Likewise.
(sse_cvtss2siq): Likewise.
(sse_cvtss2siq_2): Likewise.
(sse_cvttss2si): Likewise.
(sse_cvttss2siq): Likewise.
(sse2_cvttps2dq): Likewise.
(sse3_movshdup): Likewise.
(sse3_movsldup): Likewise.
(sse2_cvtsd2si): Likewise.
(sse2_cvtsd2si_2): Likewise.
(sse2_cvtsd2siq): Likewise.
(sse2_cvtsd2siq_2): Likewise.
(sse2_cvttsd2si): Likewise.
(sse2_cvttsd2siq): Likewise.
(*sse2_cvtpd2dq): Likewise.
(*sse2_cvttpd2dq): Likewise.
(sse2_pshuflw_1): Likewise.
(sse2_pshufhw_1): Likewise.
(sse4a_insertqi): Likewise.
(sse4a_insertq): Likewise.
(ssse3_phaddwv8hi3): Set prefix_data16 and prefix_extra.
(ssse3_phadddv4si3): Likewise.
(ssse3_phaddswv8hi3): Likewise.
(ssse3_phsubwv8hi3): Likewise.
(ssse3_phsubdv4si3): Likewise.
(ssse3_phsubswv8hi3): Likewise.
(ssse3_pmaddubswv8hi3): Likewise.
(ssse3_pmulhrswv8hi3): Likewise.
(ssse3_pshufbv16qi3): Likewise.
(ssse3_psign<mode>3): Likewise.
(ssse3_palignrti): Likewise.
(abs<mode>2): Likewise.
(ssse3_phaddwv4hi3): Set prefix_extra.
(ssse3_phadddv2si3): Likewise.
(ssse3_phaddswv4hi3): Likewise.
(ssse3_phsubwv4hi3): Likewise.
(ssse3_phsubdv2si3): Likewise.
(ssse3_phsubswv4hi3): Likewise.
(ssse3_pmaddubswv4hi3): Likewise.
(ssse3_pmulhrswv4hi3): Likewise.
(ssse3_pshufbv8qi3): Likewise.
(ssse3_psign<mode>3): Likewise.
(ssse3_palignrdi): Likewise.
(abs<mode>2): Likewise.
(sse2_cvtdq2ps): Set mode to V4SF instead of V2DF.
(*vec_dupv2df): Set mode to V2DF instead of V4SF.
(sse2_pmovmskb): Set mode to SI instead of V2DF.
--- gcc/config/i386/i386.md.length 2007-04-20 18:17:44.000000000 -0700
+++ gcc/config/i386/i386.md 2007-04-21 13:14:48.000000000 -0700
@@ -317,6 +317,9 @@
]
(const_int 0)))
+;; There are also additional prefixes in SSSE3.
+(define_attr "prefix_extra" "" (const_int 0))
+
;; Set when modrm byte is used.
(define_attr "modrm" ""
(cond [(eq_attr "type" "str,leave")
@@ -366,7 +369,8 @@
(plus (plus (attr "modrm")
(plus (attr "prefix_0f")
(plus (attr "prefix_rex")
- (const_int 1))))
+ (plus (attr "prefix_extra")
+ (const_int 1)))))
(plus (attr "prefix_rep")
(plus (attr "prefix_data16")
(plus (attr "length_immediate")
--- gcc/config/i386/sse.md.length 2007-04-17 14:05:59.000000000 -0700
+++ gcc/config/i386/sse.md 2007-04-21 14:07:48.000000000 -0700
@@ -267,6 +267,7 @@
"TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"movdqu\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse_movntv4sf"
@@ -294,6 +295,7 @@
"TARGET_SSE2"
"movntdq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_movntsi"
@@ -312,6 +314,7 @@
"TARGET_SSE3"
"lddqu\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "TI")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -650,6 +653,7 @@
"TARGET_SSE3"
"addsubps\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "V4SF")])
(define_insn "sse3_haddv4sf3"
@@ -676,6 +680,7 @@
"TARGET_SSE3"
"haddps\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "V4SF")])
(define_insn "sse3_hsubv4sf3"
@@ -702,6 +707,7 @@
"TARGET_SSE3"
"hsubps\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "V4SF")])
(define_expand "reduc_splus_v4sf"
@@ -1005,6 +1011,7 @@
"cvtss2si\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "SI")])
(define_insn "sse_cvtss2si_2"
@@ -1016,6 +1023,7 @@
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "SI")])
(define_insn "sse_cvtss2siq"
@@ -1029,6 +1037,7 @@
"cvtss2siq\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "DI")])
(define_insn "sse_cvtss2siq_2"
@@ -1040,6 +1049,7 @@
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "DI")])
(define_insn "sse_cvttss2si"
@@ -1053,6 +1063,7 @@
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "SI")])
(define_insn "sse_cvttss2siq"
@@ -1066,6 +1077,7 @@
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "DI")])
(define_insn "sse2_cvtdq2ps"
@@ -1074,7 +1086,7 @@
"TARGET_SSE2"
"cvtdq2ps\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
- (set_attr "mode" "V2DF")])
+ (set_attr "mode" "V4SF")])
(define_insn "sse2_cvtps2dq"
[(set (match_operand:V4SI 0 "register_operand" "=x")
@@ -1083,6 +1095,7 @@
"TARGET_SSE2"
"cvtps2dq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_cvttps2dq"
@@ -1091,6 +1104,7 @@
"TARGET_SSE2"
"cvttps2dq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "TI")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -1176,6 +1190,7 @@
"TARGET_SSE3"
"movshdup\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "V4SF")])
(define_insn "sse3_movsldup"
@@ -1191,6 +1206,7 @@
"TARGET_SSE3"
"movsldup\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "V4SF")])
(define_expand "sse_shufps"
@@ -1923,6 +1939,7 @@
"cvtpd2pi\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(set_attr "unit" "mmx")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "DI")])
(define_insn "sse2_cvttpd2pi"
@@ -1932,6 +1949,7 @@
"cvttpd2pi\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(set_attr "unit" "mmx")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_cvtsi2sd"
@@ -1973,6 +1991,7 @@
"cvtsd2si\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "SI")])
(define_insn "sse2_cvtsd2si_2"
@@ -1984,6 +2003,7 @@
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "SI")])
(define_insn "sse2_cvtsd2siq"
@@ -1997,6 +2017,7 @@
"cvtsd2siq\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "DI")])
(define_insn "sse2_cvtsd2siq_2"
@@ -2008,6 +2029,7 @@
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "DI")])
(define_insn "sse2_cvttsd2si"
@@ -2019,6 +2041,7 @@
"TARGET_SSE2"
"cvttsd2si\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "SI")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")])
@@ -2032,6 +2055,7 @@
"TARGET_SSE2 && TARGET_64BIT"
"cvttsd2siq\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "DI")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")])
@@ -2065,6 +2089,7 @@
"TARGET_SSE2"
"cvtpd2dq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "TI")
(set_attr "amdfam10_decode" "double")])
@@ -2084,6 +2109,7 @@
"TARGET_SSE2"
"cvttpd2dq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "TI")
(set_attr "amdfam10_decode" "double")])
@@ -2135,6 +2161,7 @@
"TARGET_SSE2"
"cvtpd2ps\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "V4SF")
(set_attr "amdfam10_decode" "double")])
@@ -2427,7 +2454,7 @@
"TARGET_SSE2"
"unpcklpd\t%0, %0"
[(set_attr "type" "sselog1")
- (set_attr "mode" "V4SF")])
+ (set_attr "mode" "V2DF")])
(define_insn "*vec_concatv2df_sse3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
@@ -2514,6 +2541,7 @@
"TARGET_SSE2 && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
"padd<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_ssadd<mode>3"
@@ -2524,6 +2552,7 @@
"TARGET_SSE2 && ix86_binary_operator_ok (SS_PLUS, <MODE>mode, operands)"
"padds<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_usadd<mode>3"
@@ -2534,6 +2563,7 @@
"TARGET_SSE2 && ix86_binary_operator_ok (US_PLUS, <MODE>mode, operands)"
"paddus<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "sub<mode>3"
@@ -2551,6 +2581,7 @@
"TARGET_SSE2"
"psub<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_sssub<mode>3"
@@ -2561,6 +2592,7 @@
"TARGET_SSE2"
"psubs<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_ussub<mode>3"
@@ -2571,6 +2603,7 @@
"TARGET_SSE2"
"psubus<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "mulv16qi3"
@@ -2631,6 +2664,7 @@
"TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
"pmullw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseimul")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "smulv8hi3_highpart"
@@ -2659,6 +2693,7 @@
"TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
"pmulhw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseimul")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "umulv8hi3_highpart"
@@ -2687,6 +2722,7 @@
"TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
"pmulhuw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseimul")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_umulv2siv2di3"
@@ -2703,6 +2739,7 @@
"TARGET_SSE2 && ix86_binary_operator_ok (MULT, V4SImode, operands)"
"pmuludq\t{%2, %0|%0, %2}"
[(set_attr "type" "sseimul")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_pmaddwd"
@@ -2739,6 +2776,7 @@
"TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
"pmaddwd\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "mulv4si3"
@@ -3037,6 +3075,7 @@
"TARGET_SSE2"
"psra<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "lshr<mode>3"
@@ -3047,6 +3086,7 @@
"TARGET_SSE2"
"psrl<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "ashl<mode>3"
@@ -3057,6 +3097,7 @@
"TARGET_SSE2"
"psll<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_ashlti3"
@@ -3069,6 +3110,7 @@
return "pslldq\t{%2, %0|%0, %2}";
}
[(set_attr "type" "sseishft")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "vec_shl_<mode>"
@@ -3093,6 +3135,7 @@
return "psrldq\t{%2, %0|%0, %2}";
}
[(set_attr "type" "sseishft")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "vec_shr_<mode>"
@@ -3121,6 +3164,7 @@
"TARGET_SSE2 && ix86_binary_operator_ok (UMAX, V16QImode, operands)"
"pmaxub\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "smaxv8hi3"
@@ -3137,6 +3181,7 @@
"TARGET_SSE2 && ix86_binary_operator_ok (SMAX, V8HImode, operands)"
"pmaxsw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "umaxv8hi3"
@@ -3206,6 +3251,7 @@
"TARGET_SSE2 && ix86_binary_operator_ok (UMIN, V16QImode, operands)"
"pminub\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "sminv8hi3"
@@ -3222,6 +3268,7 @@
"TARGET_SSE2 && ix86_binary_operator_ok (SMIN, V8HImode, operands)"
"pminsw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "smin<mode>3"
@@ -3278,6 +3325,7 @@
"TARGET_SSE2 && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
"pcmpeq<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "ssecmp")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_gt<mode>3"
@@ -3288,6 +3336,7 @@
"TARGET_SSE2"
"pcmpgt<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "ssecmp")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "vcond<mode>"
@@ -3358,6 +3407,7 @@
"TARGET_SSE2 && ix86_binary_operator_ok (AND, <MODE>mode, operands)"
"pand\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_nand<mode>3"
@@ -3368,6 +3418,7 @@
"TARGET_SSE2"
"pandn\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "ior<mode>3"
@@ -3385,6 +3436,7 @@
"TARGET_SSE2 && ix86_binary_operator_ok (IOR, <MODE>mode, operands)"
"por\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "xor<mode>3"
@@ -3402,6 +3454,7 @@
"TARGET_SSE2 && ix86_binary_operator_ok (XOR, <MODE>mode, operands)"
"pxor\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -3641,6 +3694,7 @@
"TARGET_SSE2"
"packsswb\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_packssdw"
@@ -3653,6 +3707,7 @@
"TARGET_SSE2"
"packssdw\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_packuswb"
@@ -3665,6 +3720,7 @@
"TARGET_SSE2"
"packuswb\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_punpckhbw"
@@ -3684,6 +3740,7 @@
"TARGET_SSE2"
"punpckhbw\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_punpcklbw"
@@ -3703,6 +3760,7 @@
"TARGET_SSE2"
"punpcklbw\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_punpckhwd"
@@ -3718,6 +3776,7 @@
"TARGET_SSE2"
"punpckhwd\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_punpcklwd"
@@ -3733,6 +3792,7 @@
"TARGET_SSE2"
"punpcklwd\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_punpckhdq"
@@ -3746,6 +3806,7 @@
"TARGET_SSE2"
"punpckhdq\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_punpckldq"
@@ -3759,6 +3820,7 @@
"TARGET_SSE2"
"punpckldq\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_punpckhqdq"
@@ -3772,6 +3834,7 @@
"TARGET_SSE2"
"punpckhqdq\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_punpcklqdq"
@@ -3785,6 +3848,7 @@
"TARGET_SSE2"
"punpcklqdq\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "*sse2_pinsrw"
@@ -3800,6 +3864,7 @@
return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
}
[(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "*sse2_pextrw"
@@ -3811,6 +3876,7 @@
"TARGET_SSE2"
"pextrw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "sse2_pshufd"
@@ -3848,6 +3914,7 @@
return "pshufd\t{%2, %1, %0|%0, %1, %2}";
}
[(set_attr "type" "sselog1")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_expand "sse2_pshuflw"
@@ -3889,6 +3956,7 @@
return "pshuflw\t{%2, %1, %0|%0, %1, %2}";
}
[(set_attr "type" "sselog")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "TI")])
(define_expand "sse2_pshufhw"
@@ -3930,6 +3998,7 @@
return "pshufhw\t{%2, %1, %0|%0, %1, %2}";
}
[(set_attr "type" "sselog")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "TI")])
(define_expand "sse2_loadd"
@@ -4376,6 +4445,7 @@
"TARGET_SSE2 && ix86_binary_operator_ok (PLUS, V16QImode, operands)"
"pavgb\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_uavgv8hi3"
@@ -4396,6 +4466,7 @@
"TARGET_SSE2 && ix86_binary_operator_ok (PLUS, V8HImode, operands)"
"pavgw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
;; The correct representation for this is absolutely enormous, and
@@ -4408,6 +4479,7 @@
"TARGET_SSE2"
"psadbw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse_movmskps"
@@ -4435,7 +4507,8 @@
"TARGET_SSE2"
"pmovmskb\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
- (set_attr "mode" "V2DF")])
+ (set_attr "prefix_data16" "1")
+ (set_attr "mode" "SI")])
(define_expand "sse2_maskmovdqu"
[(set (match_operand:V16QI 0 "memory_operand" "")
@@ -4456,6 +4529,7 @@
;; @@@ check ordering of operands in intel/nonintel syntax
"maskmovdqu\t{%2, %1|%1, %2}"
[(set_attr "type" "ssecvt")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "*sse2_maskmovdqu_rex64"
@@ -4468,6 +4542,7 @@
;; @@@ check ordering of operands in intel/nonintel syntax
"maskmovdqu\t{%2, %1|%1, %2}"
[(set_attr "type" "ssecvt")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse_ldmxcsr"
@@ -4618,6 +4693,8 @@
"TARGET_SSSE3"
"phaddw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
(define_insn "ssse3_phaddwv4hi3"
@@ -4644,6 +4721,7 @@
"TARGET_SSSE3"
"phaddw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "DI")])
(define_insn "ssse3_phadddv4si3"
@@ -4670,6 +4748,8 @@
"TARGET_SSSE3"
"phaddd\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
(define_insn "ssse3_phadddv2si3"
@@ -4688,6 +4768,7 @@
"TARGET_SSSE3"
"phaddd\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "DI")])
(define_insn "ssse3_phaddswv8hi3"
@@ -4730,6 +4811,8 @@
"TARGET_SSSE3"
"phaddsw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
(define_insn "ssse3_phaddswv4hi3"
@@ -4756,6 +4839,7 @@
"TARGET_SSSE3"
"phaddsw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "DI")])
(define_insn "ssse3_phsubwv8hi3"
@@ -4798,6 +4882,8 @@
"TARGET_SSSE3"
"phsubw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
(define_insn "ssse3_phsubwv4hi3"
@@ -4824,6 +4910,7 @@
"TARGET_SSSE3"
"phsubw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "DI")])
(define_insn "ssse3_phsubdv4si3"
@@ -4850,6 +4937,8 @@
"TARGET_SSSE3"
"phsubd\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
(define_insn "ssse3_phsubdv2si3"
@@ -4868,6 +4957,7 @@
"TARGET_SSSE3"
"phsubd\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "DI")])
(define_insn "ssse3_phsubswv8hi3"
@@ -4910,6 +5000,8 @@
"TARGET_SSSE3"
"phsubsw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
(define_insn "ssse3_phsubswv4hi3"
@@ -4936,6 +5028,7 @@
"TARGET_SSSE3"
"phsubsw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "DI")])
(define_insn "ssse3_pmaddubswv8hi3"
@@ -4988,6 +5081,8 @@
"TARGET_SSSE3"
"pmaddubsw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_data16" "1")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
(define_insn "ssse3_pmaddubswv4hi3"
@@ -5024,6 +5119,7 @@
"TARGET_SSSE3"
"pmaddubsw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "DI")])
(define_insn "ssse3_pmulhrswv8hi3"
@@ -5046,6 +5142,8 @@
"TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
"pmulhrsw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseimul")
+ (set_attr "prefix_data16" "1")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
(define_insn "ssse3_pmulhrswv4hi3"
@@ -5066,6 +5164,7 @@
"TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V4HImode, operands)"
"pmulhrsw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseimul")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "DI")])
(define_insn "ssse3_pshufbv16qi3"
@@ -5076,6 +5175,8 @@
"TARGET_SSSE3"
"pshufb\t{%2, %0|%0, %2}";
[(set_attr "type" "sselog1")
+ (set_attr "prefix_data16" "1")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
(define_insn "ssse3_pshufbv8qi3"
@@ -5086,6 +5187,7 @@
"TARGET_SSSE3"
"pshufb\t{%2, %0|%0, %2}";
[(set_attr "type" "sselog1")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "DI")])
(define_insn "ssse3_psign<mode>3"
@@ -5096,6 +5198,8 @@
"TARGET_SSSE3"
"psign<ssevecsize>\t{%2, %0|%0, %2}";
[(set_attr "type" "sselog1")
+ (set_attr "prefix_data16" "1")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
(define_insn "ssse3_psign<mode>3"
@@ -5106,6 +5210,7 @@
"TARGET_SSSE3"
"psign<mmxvecsize>\t{%2, %0|%0, %2}";
[(set_attr "type" "sselog1")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "DI")])
(define_insn "ssse3_palignrti"
@@ -5120,6 +5225,8 @@
return "palignr\t{%3, %2, %0|%0, %2, %3}";
}
[(set_attr "type" "sseishft")
+ (set_attr "prefix_data16" "1")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
(define_insn "ssse3_palignrdi"
@@ -5134,6 +5241,7 @@
return "palignr\t{%3, %2, %0|%0, %2, %3}";
}
[(set_attr "type" "sseishft")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "DI")])
(define_insn "abs<mode>2"
@@ -5142,6 +5250,8 @@
"TARGET_SSSE3"
"pabs<ssevecsize>\t{%1, %0|%0, %1}";
[(set_attr "type" "sselog1")
+ (set_attr "prefix_data16" "1")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
(define_insn "abs<mode>2"
@@ -5150,6 +5260,7 @@
"TARGET_SSSE3"
"pabs<mmxvecsize>\t{%1, %0|%0, %1}";
[(set_attr "type" "sselog1")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "DI")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -5207,6 +5318,7 @@
"TARGET_SSE4A"
"extrq\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "sse")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse4a_extrq"
@@ -5217,6 +5329,7 @@
"TARGET_SSE4A"
"extrq\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")
+ (set_attr "prefix_data16" "1")
(set_attr "mode" "TI")])
(define_insn "sse4a_insertqi"
@@ -5229,6 +5342,7 @@
"TARGET_SSE4A"
"insertq\t{%4, %3, %2, %0|%0, %2, %3, %4}"
[(set_attr "type" "sseins")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "TI")])
(define_insn "sse4a_insertq"
@@ -5239,4 +5353,5 @@
"TARGET_SSE4A"
"insertq\t{%2, %0|%0, %2}"
[(set_attr "type" "sseins")
+ (set_attr "prefix_rep" "1")
(set_attr "mode" "TI")])