This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: generic and i386 bswap improvements
- From: Richard Henderson <rth at redhat dot com>
- To: Uros Bizjak <ubizjak at gmail dot com>
- Cc: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Thu, 15 Feb 2007 07:33:09 -0800
- Subject: Re: generic and i386 bswap improvements
- References: <5787cf470702132321i652a4aa7lcf921894a768286@mail.gmail.com>
On Wed, Feb 14, 2007 at 08:21:30AM +0100, Uros Bizjak wrote:
> According to pentium optimization guide, this is a win only for
> pentium4 (1.5clk vs 4clk), other targets should use rolw $8, $cx or
> (rorw $8, $cx) instead of xchgb.
Huh. I wouldn't have guessed that.
> Perhaps we should generate rolw as default (it also operates on
> registers, other than Q) and split it after reload into xchgb when
> appropriate?
A good idea, particularly about the Q regs.
> -(define_insn "*rotlhi3_1"
> +(define_insn_and_split "*rotlhi3_1"
> [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
> (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
> (match_operand:QI 2 "nonmemory_operand" "I,c")))
> @@ -13025,6 +13025,13 @@
> "@
> rol{w}\t{%2, %0|%0, %2}
> rol{w}\t{%b2, %0|%0, %b2}"
> + "(TARGET_USE_XCHGB || optimize_size)
> + && reload_completed
> + && QI_REG_P (operands [0])
> + && INTVAL (operands[2]) == 8"
> + [(set (match_dup 0)
> + (bswap:HI (match_dup 1)))]
> + ""
I'd prefer you not use define_insn_and_split and just write
(define_split
[(set (match_operand:HI 0 "q_regs_operand" "")
(rotate:HI (match_dup 0) (const_int 8)))
(clobber (reg:CC FLAGS_REG))]
"(TARGET_USE_XCHGB || optimize_size) && reload_completed"
[(set (match_dup 0) (bswap:HI (match_dup 0)))]
"")
and you should arrange something for bswaphi_lowpart as well.
r~