RE: [patch] tuning gcc for AMDFAM10 processor (patch 1)

["Jagasia, Harsha" <harsha dot jagasia at amd dot com>]

Hi Andi,
>> This is the 1st of 11 patches to tune gcc for AMD's AMDFAM10
processor
>> (based on mainline rev 121295). This patch defines march=amdfam10 and
>> adds built-ins and intrinsics for the new instructions as needed.
>
>>+#ifdef __x86_64__
>>+  __asm__ ("pushq %%rcx; pushq %%rbx; cpuid; popq %%rbx; popq %%rcx"
>>+	   : "=a" (fl1) : "0" (0x80000000) : "rdx", "cc");
>>+#else
>>+  __asm__ ("pushl %%ecx; pushl %%ebx; cpuid; popl %%ebx; popl %%ecx"
>>+	   : "=a" (fl1) : "0" (0x80000000) : "edx", "cc");
>>+#endif
>
>You could do without the ifdef when you put ecx,ebx,edx into the
clobber
>list (32bit clobber implies 64bit one on x86-64)
>Also I didn't think either push/pop nor cpuid changed cc.

Ok, we are looking into fixing this.

>Also I was wondering how hard it would be to make gcc detect code
>patterns automatically for the new bitfield instructions?

We are looking to submit a patch before stage 2 closes that can use the
new extractq/insertq instructions for zero_extract, but we are not sure
how viable it will be because these are SSEx instructions. But, I am not
sure if you were referring to that or to auto generating popcnt/lzcnt
instructions, which happen to be integer instructions. Can you give us
some more details on what will be useful for you so we can target the
appropriate instructions and come up with the right patterns?

Thanks,
Harsha