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Re: [RTL, ColdFire 24/63] Add support for a MODE_INDEX_REG_CLASS macro
On Wed, 2007-01-10 at 11:23 +0000, Richard Sandiford wrote:
> At the moment, gcc expects there to be a single INDEX_REG_CLASS that
> applies to all MEM modes. This is not true when using a ColdFire FPU,
> as index registers are not allowed for floating-point modes. The port
> tries to hack around this by using "<Q>U" instead of "m" in the movsf
> constraints, but that's only a half solution. If reload has to reload
> an indexed MEM (rather than the MEM's address), it will expect that
> instruction to match.
>
> The fix is to allow the class of index register to vary depending on
> the mode of the addressed value, as the base register class already can.
>
> This patch does the target-independent bit. It adds new target macros
> called MODE_INDEX_REG_CLASS and REGNO_MODE_OK_FOR_INDEX_P, to accompany
> the existing MODE_BASE_REG_CLASS and REGNO_MODE_OK_FOR_BASE_P. It also
> defines index equivalents of the addresses.h base functions. This is
> all a direct image of the base register code (including the wording
> of comments and documentation). I think the two should be consistent.
> The patch then adjusts all code to use thse new addresses.h functions.
>
> Bootstrapped & regression-tested on x86_64-linux-gnu.
Umm, I'm not sure this is safe, though maybe I'm misunderstanding
something.
The fundamental problem as I see it is that there are addressing
modes which are sometimes valid and sometimes not valid. In this
particular case whether or not the addressing mode is valid is a
function of whether or not the load/store is an FPU load/store.
Your solution is to allow GCC to peek at the mode (of the MEM?) to
determine address validity -- but that's not right. The mode of the
MEM is not a reliable indicator of whether or not we're using a
floating point load/store. ie, it is possible to have an integer
mode load/store using FP load/store instructions or an floating
point mode load/store using integer load/store instructions.
Jeff