Index: gcc/gcc/ChangeLog =================================================================== --- gcc/gcc/ChangeLog (revision 119531) +++ gcc/gcc/ChangeLog (working copy) @@ -1,3 +1,14 @@ +2006-12-04 Trevor Smigiel + + * config/spu/spu-protos.c (spu_split_address): Add. + * config/spu/spu.c (spu_split_address): Add. + (print_operand): Handle HIGH. + (spu_legitimate_address): Don't test for aligned CONST. + (spu_expand_mov): Don't split addresses here. + * config/spu/constraints.md (A): Don't test legitimate_const. + * config/spu/spu.md: Add split of movsi patterns for PIC mode. + (ceq_di): Use correct predicates. + 2006-12-04 Eric Christopher * config/darwin.h: Update copyright notice. Index: gcc/gcc/config/spu/spu-protos.h =================================================================== --- gcc/gcc/config/spu/spu-protos.h (revision 119531) +++ gcc/gcc/config/spu/spu-protos.h (working copy) @@ -34,6 +34,7 @@ extern HOST_WIDE_INT const_double_to_hwi extern rtx hwint_to_const_double (enum machine_mode mode, HOST_WIDE_INT v); extern void print_operand_address (FILE * file, register rtx addr); extern void print_operand (FILE * file, rtx x, int code); +extern void spu_split_address (rtx * ops); extern int spu_saved_regs_size (void); extern int direct_return (void); extern void spu_expand_prologue (void); Index: gcc/gcc/config/spu/spu.c =================================================================== --- gcc/gcc/config/spu/spu.c (revision 119531) +++ gcc/gcc/config/spu/spu.c (working copy) @@ -1088,6 +1088,8 @@ print_operand (FILE * file, rtx x, int c } else if (xcode == SYMBOL_REF || xcode == LABEL_REF || xcode == CONST) fprintf (file, "a"); + else if (xcode == HIGH) + fprintf (file, "hu"); else gcc_unreachable (); return; @@ -1118,6 +1120,11 @@ print_operand (FILE * file, rtx x, int c } else if (xcode == CONST || xcode == SYMBOL_REF || xcode == LABEL_REF) output_addr_const (file, x); + else if (xcode == HIGH) + { + output_addr_const (file, XEXP (x, 0)); + fprintf (file, "@h"); + } else gcc_unreachable (); return; @@ -1267,6 +1274,27 @@ get_pic_reg (void) return pic_reg; } +/* Split constant addresses to handle cases that are too large. Also, add in + the pic register when in PIC mode. */ +void +spu_split_address (rtx * ops) +{ + if (TARGET_LARGE_MEM + || (GET_CODE (ops[1]) == CONST && !legitimate_const (ops[1], 0))) + { + emit_insn (gen_high (ops[0], ops[1])); + emit_insn (gen_low (ops[0], ops[0], ops[1])); + } + else if (flag_pic) + emit_insn (gen_pic (ops[0], ops[1])); + if (flag_pic) + { + rtx pic_reg = get_pic_reg (); + emit_insn (gen_addsi3 (ops[0], ops[0], pic_reg)); + current_function_uses_pic_offset_table = 1; + } +} + /* SAVING is TRUE when we are generating the actual load and store instructions for REGNO. When determining the size of the stack needed for saving register we must allocate enough space for the @@ -2408,7 +2436,7 @@ spu_legitimate_address (enum machine_mod return !TARGET_LARGE_MEM; case CONST: - return !TARGET_LARGE_MEM && legitimate_const (x, 1); + return !TARGET_LARGE_MEM && legitimate_const (x, 0); case CONST_INT: return INTVAL (x) >= 0 && INTVAL (x) <= 0x3ffff; @@ -3091,34 +3119,6 @@ spu_expand_mov (rtx * ops, enum machine_ emit_insn (gen_rtx_SET (VOIDmode, to, gen_rtx_IOR (mode, to, lo))); return 1; } - if ((GET_CODE (ops[1]) == CONST - && !legitimate_const (ops[1], 0)) - || (TARGET_LARGE_MEM - && (GET_CODE (ops[1]) == CONST - || GET_CODE (ops[1]) == SYMBOL_REF - || GET_CODE (ops[1]) == LABEL_REF))) - { - emit_insn (gen_high (ops[0], ops[1])); - emit_insn (gen_low (ops[0], ops[0], ops[1])); - if (flag_pic) - { - rtx pic_reg = get_pic_reg (); - emit_insn (gen_addsi3 (ops[0], ops[0], pic_reg)); - current_function_uses_pic_offset_table = 1; - } - return 1; - } - if (flag_pic - && (GET_CODE (ops[1]) == SYMBOL_REF - || GET_CODE (ops[1]) == LABEL_REF - || GET_CODE (ops[1]) == CONST)) - { - rtx pic_reg = get_pic_reg (); - emit_insn (gen_pic (ops[0], ops[1])); - emit_insn (gen_addsi3 (ops[0], ops[0], pic_reg)); - current_function_uses_pic_offset_table = 1; - return 1; - } return 0; } else Index: gcc/gcc/config/spu/constraints.md =================================================================== --- gcc/gcc/config/spu/constraints.md (revision 119531) +++ gcc/gcc/config/spu/constraints.md (working copy) @@ -28,10 +28,7 @@ (define_constraint "A" "An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value." (ior (and (match_code "const_int,const_double,const_vector") (match_test "immediate_load_p (op, SImode)")) - (and (match_test "!TARGET_LARGE_MEM && !flag_pic") - (ior (match_code "symbol_ref,label_ref") - (and (match_code "const") - (match_test "legitimate_const (op, 0)")))))) + (match_code "symbol_ref,label_ref,high,const"))) (define_constraint "B" "An immediate for arithmetic instructions (e.g., ai, ceqi). const_int is treated as a 32 bit value." Index: gcc/gcc/config/spu/spu.md =================================================================== --- gcc/gcc/config/spu/spu.md (revision 119531) +++ gcc/gcc/config/spu/spu.md (working copy) @@ -237,6 +237,29 @@ (define_expand "mov" DONE; }) +(define_split + [(set (match_operand:SI 0 "spu_reg_operand" "=r") + (match_operand:SI 1 "immediate_operand" "s"))] + + "(flag_pic || TARGET_LARGE_MEM + || (GET_CODE (operands[1]) == CONST + && !legitimate_const (operands[1], 0))) + && (reload_in_progress || reload_completed) + && (GET_CODE (operands[1]) == CONST + || GET_CODE (operands[1]) == SYMBOL_REF + || GET_CODE (operands[1]) == LABEL_REF)" + [(parallel + [(set (match_dup:SI 0) + (match_dup:SI 1)) + (use (const_int 0))]) + (set (match_dup:SI 0) + (plus:SI (match_dup:SI 0) + (match_dup:SI 2)))] + { + spu_split_address(operands); + DONE; + }) + (define_insn "pic" [(set (match_operand:SI 0 "spu_reg_operand" "=r") (match_operand:SI 1 "immediate_operand" "s")) @@ -2408,9 +2431,9 @@ (define_insn "ceq_" ceqi\t%0,%1,%2") (define_insn_and_split "ceq_di" - [(set (match_operand:SI 0 "register_operand" "=r") - (eq:SI (match_operand:DI 1 "register_operand" "r") - (match_operand:DI 2 "register_operand" "r")))] + [(set (match_operand:SI 0 "spu_reg_operand" "=r") + (eq:SI (match_operand:DI 1 "spu_reg_operand" "r") + (match_operand:DI 2 "spu_reg_operand" "r")))] "" "#" "reload_completed"