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[PATCH] PR29166: Fix bad prologue generation on ia64
- From: Andreas Schwab <schwab at suse dot de>
- To: gcc-patches at gcc dot gnu dot org
- Date: Fri, 24 Nov 2006 23:18:43 +0100
- Subject: [PATCH] PR29166: Fix bad prologue generation on ia64
This fixes the prologue generation on ia64. The problem is that the
return pointer is saved between the general registers and the branch
registers, causing it to wind up in the middle of the gr/br/fr spill area
when it is saved to memory. When any of the preserved general registers
need to be spilled as well the location of these regsisters is off-by-8
compared to the location described by the unwind information.
Regtested on ia64-suse-linux. OK for trunk/4.2 branch?
:ADDPATCH target/ia64:
Andreas.
2006-11-24 Andreas Schwab <schwab@suse.de>
PR target/29166
* config/ia64/ia64.c (ia64_compute_frame_size): Account space for
save of BR0 in extra_spill_size instead of spill_size.
(ia64_expand_prologue): Save BR0 outside of the gr/br/fr spill
area.
(ia64_expand_epilogue): Restore BR0 from its new location.
testsuite/:
* g++.dg/eh/pr29166.C: New test.
Index: gcc/config/ia64/ia64.c
===================================================================
--- gcc/config/ia64/ia64.c (revision 119149)
+++ gcc/config/ia64/ia64.c (working copy)
@@ -2457,7 +2457,7 @@ ia64_compute_frame_size (HOST_WIDE_INT s
current_frame_info.reg_save_b0 = find_gr_spill (1);
if (current_frame_info.reg_save_b0 == 0)
{
- spill_size += 8;
+ extra_spill_size += 8;
n_spilled += 1;
}
@@ -2486,7 +2486,7 @@ ia64_compute_frame_size (HOST_WIDE_INT s
if (regs_ever_live[BR_REG (0)] && ! call_used_regs[BR_REG (0)])
{
SET_HARD_REG_BIT (mask, BR_REG (0));
- spill_size += 8;
+ extra_spill_size += 8;
n_spilled += 1;
}
@@ -3176,6 +3176,31 @@ ia64_expand_prologue (void)
}
}
+ /* Save the return pointer. */
+ if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
+ {
+ reg = gen_rtx_REG (DImode, BR_REG (0));
+ if (current_frame_info.reg_save_b0 != 0)
+ {
+ alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
+ insn = emit_move_insn (alt_reg, reg);
+ RTX_FRAME_RELATED_P (insn) = 1;
+
+ /* Even if we're not going to generate an epilogue, we still
+ need to save the register so that EH works. */
+ if (! epilogue_p)
+ emit_insn (gen_prologue_use (alt_reg));
+ }
+ else
+ {
+ alt_regno = next_scratch_gr_reg ();
+ alt_reg = gen_rtx_REG (DImode, alt_regno);
+ emit_move_insn (alt_reg, reg);
+ do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
+ cfa_off -= 8;
+ }
+ }
+
if (current_frame_info.reg_save_gp)
{
insn = emit_move_insn (gen_rtx_REG (DImode,
@@ -3202,32 +3227,6 @@ ia64_expand_prologue (void)
cfa_off -= 8;
}
- /* Handle BR0 specially -- it may be getting stored permanently in
- some GR register. */
- if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
- {
- reg = gen_rtx_REG (DImode, BR_REG (0));
- if (current_frame_info.reg_save_b0 != 0)
- {
- alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
- insn = emit_move_insn (alt_reg, reg);
- RTX_FRAME_RELATED_P (insn) = 1;
-
- /* Even if we're not going to generate an epilogue, we still
- need to save the register so that EH works. */
- if (! epilogue_p)
- emit_insn (gen_prologue_use (alt_reg));
- }
- else
- {
- alt_regno = next_scratch_gr_reg ();
- alt_reg = gen_rtx_REG (DImode, alt_regno);
- emit_move_insn (alt_reg, reg);
- do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
- cfa_off -= 8;
- }
- }
-
/* Spill the rest of the BR registers. */
for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
@@ -3361,6 +3360,22 @@ ia64_expand_epilogue (int sibcall_p)
emit_move_insn (reg, alt_reg);
}
+ /* Restore the return pointer. */
+ if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
+ {
+ if (current_frame_info.reg_save_b0 != 0)
+ alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
+ else
+ {
+ alt_regno = next_scratch_gr_reg ();
+ alt_reg = gen_rtx_REG (DImode, alt_regno);
+ do_restore (gen_movdi_x, alt_reg, cfa_off);
+ cfa_off -= 8;
+ }
+ reg = gen_rtx_REG (DImode, BR_REG (0));
+ emit_move_insn (reg, alt_reg);
+ }
+
/* We should now be at the base of the gr/br/fr spill area. */
gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
+ current_frame_info.spill_size));
@@ -3379,23 +3394,7 @@ ia64_expand_epilogue (int sibcall_p)
cfa_off -= 8;
}
- /* Restore the branch registers. Handle B0 specially, as it may
- have gotten stored in some GR register. */
- if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
- {
- if (current_frame_info.reg_save_b0 != 0)
- alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
- else
- {
- alt_regno = next_scratch_gr_reg ();
- alt_reg = gen_rtx_REG (DImode, alt_regno);
- do_restore (gen_movdi_x, alt_reg, cfa_off);
- cfa_off -= 8;
- }
- reg = gen_rtx_REG (DImode, BR_REG (0));
- emit_move_insn (reg, alt_reg);
- }
-
+ /* Restore the branch registers. */
for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
{
--- /dev/null 2006-06-02 16:57:24.000000000 +0200
+++ gcc/testsuite/g++.dg/eh/pr29166.C 2006-11-24 23:10:18.000000000 +0100
@@ -0,0 +1,197 @@
+// PR 29166: r4-r7 corrupted when unwinding.
+// { dg-do run }
+
+class Ex
+{
+public:
+ int val;
+
+ Ex( int v )
+ : val( v )
+ { }
+
+};
+
+void doIt()
+{
+ int OFF( 1000 );
+ register int v1=OFF+1,v2=OFF+2,v3=OFF+3,v4=OFF+4,v5=OFF+5,v6=OFF+6,v7=OFF+7,v8=OFF+8,v9=OFF+9,v10=OFF+10;
+ register int v11=OFF+11,v12=OFF+12,v13=OFF+13,v14=OFF+14,v15=OFF+15,v16=OFF+16,v17=OFF+17,v18=OFF+18,v19=OFF+19,v20=OFF+20;
+ register int v21=OFF+21,v22=OFF+22,v23=OFF+23,v24=OFF+24,v25=OFF+25,v26=OFF+26,v27=OFF+27,v28=OFF+28,v29=OFF+29,v30=OFF+30;
+ register int v31=OFF+31,v32=OFF+32,v33=OFF+33,v34=OFF+34,v35=OFF+35,v36=OFF+36,v37=OFF+37,v38=OFF+38,v39=OFF+39,v40=OFF+40;
+ register int v41=OFF+41,v42=OFF+42,v43=OFF+43,v44=OFF+44,v45=OFF+45,v46=OFF+46,v47=OFF+47,v48=OFF+48,v49=OFF+49,v50=OFF+50;
+ register int v51=OFF+51,v52=OFF+52,v53=OFF+53,v54=OFF+54,v55=OFF+55,v56=OFF+56,v57=OFF+57,v58=OFF+58,v59=OFF+59,v60=OFF+60;
+ register int v61=OFF+61,v62=OFF+62,v63=OFF+63,v64=OFF+64,v65=OFF+65,v66=OFF+66,v67=OFF+67,v68=OFF+68,v69=OFF+69,v70=OFF+70;
+ register int v71=OFF+71,v72=OFF+72,v73=OFF+73,v74=OFF+74,v75=OFF+75,v76=OFF+76,v77=OFF+77,v78=OFF+78,v79=OFF+79,v80=OFF+80;
+ register int v81=OFF+81,v82=OFF+82,v83=OFF+83,v84=OFF+84,v85=OFF+85,v86=OFF+86,v87=OFF+87,v88=OFF+88,v89=OFF+89,v90=OFF+90;
+ register int v91=OFF+91,v92=OFF+92,v93=OFF+93,v94=OFF+94,v95=OFF+95,v96=OFF+96,v97=OFF+97,v98=OFF+98,v99=OFF+99,v100=OFF+100;
+ register int v101=OFF+101,v102=OFF+102,v103=OFF+103,v104=OFF+104,v105=OFF+105,v106=OFF+106,v107=OFF+107,v108=OFF+108,v109=OFF+109,v110=OFF+110;
+ register int v111=OFF+111,v112=OFF+112,v113=OFF+113,v114=OFF+114,v115=OFF+115,v116=OFF+116,v117=OFF+117,v118=OFF+118,v119=OFF+119,v120=OFF+120;
+ register int v121=OFF+121,v122=OFF+122,v123=OFF+123,v124=OFF+124,v125=OFF+125,v126=OFF+126,v127=OFF+127,v128=OFF+128,v129=OFF+129,v130=OFF+130;
+ register int v131=OFF+131,v132=OFF+132,v133=OFF+133,v134=OFF+134,v135=OFF+135,v136=OFF+136,v137=OFF+137,v138=OFF+138,v139=OFF+139,v140=OFF+140;
+ register int v141=OFF+141,v142=OFF+142,v143=OFF+143,v144=OFF+144,v145=OFF+145,v146=OFF+146,v147=OFF+147,v148=OFF+148,v149=OFF+149,v150=OFF+150;
+ register int v151=OFF+151,v152=OFF+152,v153=OFF+153,v154=OFF+154,v155=OFF+155,v156=OFF+156,v157=OFF+157,v158=OFF+158,v159=OFF+159,v160=OFF+160;
+ register int v161=OFF+161,v162=OFF+162,v163=OFF+163,v164=OFF+164,v165=OFF+165,v166=OFF+166,v167=OFF+167,v168=OFF+168,v169=OFF+169,v170=OFF+170;
+ register int v171=OFF+171,v172=OFF+172,v173=OFF+173,v174=OFF+174,v175=OFF+175,v176=OFF+176,v177=OFF+177,v178=OFF+178,v179=OFF+179,v180=OFF+180;
+ register int v181=OFF+181,v182=OFF+182,v183=OFF+183,v184=OFF+184,v185=OFF+185,v186=OFF+186,v187=OFF+187,v188=OFF+188,v189=OFF+189,v190=OFF+190;
+ register int v191=OFF+191,v192=OFF+192,v193=OFF+193,v194=OFF+194,v195=OFF+195,v196=OFF+196,v197=OFF+197,v198=OFF+198,v199=OFF+199,v200=OFF+200;
+ register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OFF+207,v208=OFF+208,v209=OFF+209,v210=OFF+210;
+ register int v211=OFF+211,v212=OFF+212,v213=OFF+213,v214=OFF+214,v215=OFF+215,v216=OFF+216,v217=OFF+217,v218=OFF+218,v219=OFF+219,v220=OFF+220;
+ register int v231=OFF+231,v232=OFF+232,v233=OFF+233,v234=OFF+234,v235=OFF+235,v236=OFF+236,v237=OFF+237,v238=OFF+238,v239=OFF+239,v240=OFF+240;
+ register int v241=OFF+241,v242=OFF+242,v243=OFF+243,v244=OFF+244,v245=OFF+245,v246=OFF+246,v247=OFF+247,v248=OFF+248,v249=OFF+249,v250=OFF+250;
+ register int v251=OFF+251,v252=OFF+252,v253=OFF+253,v254=OFF+254,v255=OFF+255,v256=OFF+256,v257=OFF+257,v258=OFF+258,v259=OFF+259,v260=OFF+260;
+ register int v261=OFF+261,v262=OFF+262,v263=OFF+263,v264=OFF+264,v265=OFF+265,v266=OFF+266,v267=OFF+267,v268=OFF+268,v269=OFF+269,v270=OFF+270;
+ register int v271=OFF+271,v272=OFF+272,v273=OFF+273,v274=OFF+274,v275=OFF+275,v276=OFF+276,v277=OFF+277,v278=OFF+278,v279=OFF+279,v280=OFF+280;
+ register int v281=OFF+281,v282=OFF+282,v283=OFF+283,v284=OFF+284,v285=OFF+285,v286=OFF+286,v287=OFF+287,v288=OFF+288,v289=OFF+289,v290=OFF+290;
+ register int v291=OFF+291,v292=OFF+292,v293=OFF+293,v294=OFF+294,v295=OFF+295,v296=OFF+296,v297=OFF+297,v298=OFF+298,v299=OFF+299,v300=OFF+300;
+
+ register int sum = 0;
+ sum +=v1+v2+v3+v4+v5+v6+v7+v8+v9+v10;
+ sum +=v11+v12+v13+v14+v15+v16+v17+v18+v19+v20;
+ sum +=v21+v22+v23+v24+v25+v26+v27+v28+v29+v30;
+ sum +=v31+v32+v33+v34+v35+v36+v37+v38+v39+v40;
+ sum +=v41+v42+v43+v44+v45+v46+v47+v48+v49+v50;
+ sum +=v51+v52+v53+v54+v55+v56+v57+v58+v59+v60;
+ sum +=v61+v62+v63+v64+v65+v66+v67+v68+v69+v70;
+ sum +=v71+v72+v73+v74+v75+v76+v77+v78+v79+v80;
+ sum +=v81+v82+v83+v84+v85+v86+v87+v88+v89+v90;
+ sum +=v91+v92+v93+v94+v95+v96+v97+v98+v99+v100;
+ sum +=v101+v102+v103+v104+v105+v106+v107+v108+v109+v110;
+ sum +=v111+v112+v113+v114+v115+v116+v117+v118+v119+v120;
+ sum +=v121+v122+v123+v124+v125+v126+v127+v128+v129+v130;
+ sum +=v131+v132+v133+v134+v135+v136+v137+v138+v139+v140;
+ sum +=v141+v142+v143+v144+v145+v146+v147+v148+v149+v150;
+ sum +=v151+v152+v153+v154+v155+v156+v157+v158+v159+v160;
+ sum +=v161+v162+v163+v164+v165+v166+v167+v168+v169+v170;
+ sum +=v171+v172+v173+v174+v175+v176+v177+v178+v179+v180;
+ sum +=v181+v182+v183+v184+v185+v186+v187+v188+v189+v190;
+ sum +=v191+v192+v193+v194+v195+v196+v197+v198+v199+v200;
+ sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210;
+ sum +=v211+v212+v213+v214+v215+v216+v217+v218+v219+v220;
+ sum +=v231+v232+v233+v234+v235+v236+v237+v238+v239+v240;
+ sum +=v241+v242+v243+v244+v245+v246+v247+v248+v249+v250;
+ sum +=v251+v252+v253+v254+v255+v256+v257+v258+v259+v260;
+ sum +=v261+v262+v263+v264+v265+v266+v267+v268+v269+v270;
+ sum +=v271+v272+v273+v274+v275+v276+v277+v278+v279+v280;
+ sum +=v281+v282+v283+v284+v285+v286+v287+v288+v289+v290;
+ sum +=v291+v292+v293+v294+v295+v296+v297+v298+v299+v300;
+
+ throw Ex( sum );
+}
+
+void test()
+{
+ try {
+ doIt();
+ } catch( Ex& ) { }
+}
+
+int main(int argc, char** argv)
+{
+ int OFF(0);
+ register int v1=OFF+1,v2=OFF+2,v3=OFF+3,v4=OFF+4,v5=OFF+5,v6=OFF+6,v7=OFF+7,v8=OFF+8,v9=OFF+9,v10=OFF+10;
+ register int v11=OFF+11,v12=OFF+12,v13=OFF+13,v14=OFF+14,v15=OFF+15,v16=OFF+16,v17=OFF+17,v18=OFF+18,v19=OFF+19,v20=OFF+20;
+ register int v21=OFF+21,v22=OFF+22,v23=OFF+23,v24=OFF+24,v25=OFF+25,v26=OFF+26,v27=OFF+27,v28=OFF+28,v29=OFF+29,v30=OFF+30;
+ register int v31=OFF+31,v32=OFF+32,v33=OFF+33,v34=OFF+34,v35=OFF+35,v36=OFF+36,v37=OFF+37,v38=OFF+38,v39=OFF+39,v40=OFF+40;
+ register int v41=OFF+41,v42=OFF+42,v43=OFF+43,v44=OFF+44,v45=OFF+45,v46=OFF+46,v47=OFF+47,v48=OFF+48,v49=OFF+49,v50=OFF+50;
+ register int v51=OFF+51,v52=OFF+52,v53=OFF+53,v54=OFF+54,v55=OFF+55,v56=OFF+56,v57=OFF+57,v58=OFF+58,v59=OFF+59,v60=OFF+60;
+ register int v61=OFF+61,v62=OFF+62,v63=OFF+63,v64=OFF+64,v65=OFF+65,v66=OFF+66,v67=OFF+67,v68=OFF+68,v69=OFF+69,v70=OFF+70;
+ register int v71=OFF+71,v72=OFF+72,v73=OFF+73,v74=OFF+74,v75=OFF+75,v76=OFF+76,v77=OFF+77,v78=OFF+78,v79=OFF+79,v80=OFF+80;
+ register int v81=OFF+81,v82=OFF+82,v83=OFF+83,v84=OFF+84,v85=OFF+85,v86=OFF+86,v87=OFF+87,v88=OFF+88,v89=OFF+89,v90=OFF+90;
+ register int v91=OFF+91,v92=OFF+92,v93=OFF+93,v94=OFF+94,v95=OFF+95,v96=OFF+96,v97=OFF+97,v98=OFF+98,v99=OFF+99,v100=OFF+100;
+ register int v101=OFF+101,v102=OFF+102,v103=OFF+103,v104=OFF+104,v105=OFF+105,v106=OFF+106,v107=OFF+107,v108=OFF+108,v109=OFF+109,v110=OFF+110;
+ register int v111=OFF+111,v112=OFF+112,v113=OFF+113,v114=OFF+114,v115=OFF+115,v116=OFF+116,v117=OFF+117,v118=OFF+118,v119=OFF+119,v120=OFF+120;
+ register int v121=OFF+121,v122=OFF+122,v123=OFF+123,v124=OFF+124,v125=OFF+125,v126=OFF+126,v127=OFF+127,v128=OFF+128,v129=OFF+129,v130=OFF+130;
+ register int v131=OFF+131,v132=OFF+132,v133=OFF+133,v134=OFF+134,v135=OFF+135,v136=OFF+136,v137=OFF+137,v138=OFF+138,v139=OFF+139,v140=OFF+140;
+ register int v141=OFF+141,v142=OFF+142,v143=OFF+143,v144=OFF+144,v145=OFF+145,v146=OFF+146,v147=OFF+147,v148=OFF+148,v149=OFF+149,v150=OFF+150;
+ register int v151=OFF+151,v152=OFF+152,v153=OFF+153,v154=OFF+154,v155=OFF+155,v156=OFF+156,v157=OFF+157,v158=OFF+158,v159=OFF+159,v160=OFF+160;
+ register int v161=OFF+161,v162=OFF+162,v163=OFF+163,v164=OFF+164,v165=OFF+165,v166=OFF+166,v167=OFF+167,v168=OFF+168,v169=OFF+169,v170=OFF+170;
+ register int v171=OFF+171,v172=OFF+172,v173=OFF+173,v174=OFF+174,v175=OFF+175,v176=OFF+176,v177=OFF+177,v178=OFF+178,v179=OFF+179,v180=OFF+180;
+ register int v181=OFF+181,v182=OFF+182,v183=OFF+183,v184=OFF+184,v185=OFF+185,v186=OFF+186,v187=OFF+187,v188=OFF+188,v189=OFF+189,v190=OFF+190;
+ register int v191=OFF+191,v192=OFF+192,v193=OFF+193,v194=OFF+194,v195=OFF+195,v196=OFF+196,v197=OFF+197,v198=OFF+198,v199=OFF+199,v200=OFF+200;
+ register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OFF+207,v208=OFF+208,v209=OFF+209,v210=OFF+210;
+ register int v211=OFF+211,v212=OFF+212,v213=OFF+213,v214=OFF+214,v215=OFF+215,v216=OFF+216,v217=OFF+217,v218=OFF+218,v219=OFF+219,v220=OFF+220;
+ register int v231=OFF+231,v232=OFF+232,v233=OFF+233,v234=OFF+234,v235=OFF+235,v236=OFF+236,v237=OFF+237,v238=OFF+238,v239=OFF+239,v240=OFF+240;
+ register int v241=OFF+241,v242=OFF+242,v243=OFF+243,v244=OFF+244,v245=OFF+245,v246=OFF+246,v247=OFF+247,v248=OFF+248,v249=OFF+249,v250=OFF+250;
+ register int v251=OFF+251,v252=OFF+252,v253=OFF+253,v254=OFF+254,v255=OFF+255,v256=OFF+256,v257=OFF+257,v258=OFF+258,v259=OFF+259,v260=OFF+260;
+ register int v261=OFF+261,v262=OFF+262,v263=OFF+263,v264=OFF+264,v265=OFF+265,v266=OFF+266,v267=OFF+267,v268=OFF+268,v269=OFF+269,v270=OFF+270;
+ register int v271=OFF+271,v272=OFF+272,v273=OFF+273,v274=OFF+274,v275=OFF+275,v276=OFF+276,v277=OFF+277,v278=OFF+278,v279=OFF+279,v280=OFF+280;
+ register int v281=OFF+281,v282=OFF+282,v283=OFF+283,v284=OFF+284,v285=OFF+285,v286=OFF+286,v287=OFF+287,v288=OFF+288,v289=OFF+289,v290=OFF+290;
+ register int v291=OFF+291,v292=OFF+292,v293=OFF+293,v294=OFF+294,v295=OFF+295,v296=OFF+296,v297=OFF+297,v298=OFF+298,v299=OFF+299,v300=OFF+300;
+
+ int sum_before, sum_after;
+
+ {
+ int sum( 0 );
+ sum +=v1+v2+v3+v4+v5+v6+v7+v8+v9+v10;
+ sum +=v11+v12+v13+v14+v15+v16+v17+v18+v19+v20;
+ sum +=v21+v22+v23+v24+v25+v26+v27+v28+v29+v30;
+ sum +=v31+v32+v33+v34+v35+v36+v37+v38+v39+v40;
+ sum +=v41+v42+v43+v44+v45+v46+v47+v48+v49+v50;
+ sum +=v51+v52+v53+v54+v55+v56+v57+v58+v59+v60;
+ sum +=v61+v62+v63+v64+v65+v66+v67+v68+v69+v70;
+ sum +=v71+v72+v73+v74+v75+v76+v77+v78+v79+v80;
+ sum +=v81+v82+v83+v84+v85+v86+v87+v88+v89+v90;
+ sum +=v91+v92+v93+v94+v95+v96+v97+v98+v99+v100;
+ sum +=v101+v102+v103+v104+v105+v106+v107+v108+v109+v110;
+ sum +=v111+v112+v113+v114+v115+v116+v117+v118+v119+v120;
+ sum +=v121+v122+v123+v124+v125+v126+v127+v128+v129+v130;
+ sum +=v131+v132+v133+v134+v135+v136+v137+v138+v139+v140;
+ sum +=v141+v142+v143+v144+v145+v146+v147+v148+v149+v150;
+ sum +=v151+v152+v153+v154+v155+v156+v157+v158+v159+v160;
+ sum +=v161+v162+v163+v164+v165+v166+v167+v168+v169+v170;
+ sum +=v171+v172+v173+v174+v175+v176+v177+v178+v179+v180;
+ sum +=v181+v182+v183+v184+v185+v186+v187+v188+v189+v190;
+ sum +=v191+v192+v193+v194+v195+v196+v197+v198+v199+v200;
+ sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210;
+ sum +=v211+v212+v213+v214+v215+v216+v217+v218+v219+v220;
+ sum +=v231+v232+v233+v234+v235+v236+v237+v238+v239+v240;
+ sum +=v241+v242+v243+v244+v245+v246+v247+v248+v249+v250;
+ sum +=v251+v252+v253+v254+v255+v256+v257+v258+v259+v260;
+ sum +=v261+v262+v263+v264+v265+v266+v267+v268+v269+v270;
+ sum +=v271+v272+v273+v274+v275+v276+v277+v278+v279+v280;
+ sum +=v281+v282+v283+v284+v285+v286+v287+v288+v289+v290;
+ sum +=v291+v292+v293+v294+v295+v296+v297+v298+v299+v300;
+
+ sum_before = sum;
+ }
+
+ test();
+
+ {
+ int sum( 0 );
+ sum +=v1+v2+v3+v4+v5+v6+v7+v8+v9+v10;
+ sum +=v11+v12+v13+v14+v15+v16+v17+v18+v19+v20;
+ sum +=v21+v22+v23+v24+v25+v26+v27+v28+v29+v30;
+ sum +=v31+v32+v33+v34+v35+v36+v37+v38+v39+v40;
+ sum +=v41+v42+v43+v44+v45+v46+v47+v48+v49+v50;
+ sum +=v51+v52+v53+v54+v55+v56+v57+v58+v59+v60;
+ sum +=v61+v62+v63+v64+v65+v66+v67+v68+v69+v70;
+ sum +=v71+v72+v73+v74+v75+v76+v77+v78+v79+v80;
+ sum +=v81+v82+v83+v84+v85+v86+v87+v88+v89+v90;
+ sum +=v91+v92+v93+v94+v95+v96+v97+v98+v99+v100;
+ sum +=v101+v102+v103+v104+v105+v106+v107+v108+v109+v110;
+ sum +=v111+v112+v113+v114+v115+v116+v117+v118+v119+v120;
+ sum +=v121+v122+v123+v124+v125+v126+v127+v128+v129+v130;
+ sum +=v131+v132+v133+v134+v135+v136+v137+v138+v139+v140;
+ sum +=v141+v142+v143+v144+v145+v146+v147+v148+v149+v150;
+ sum +=v151+v152+v153+v154+v155+v156+v157+v158+v159+v160;
+ sum +=v161+v162+v163+v164+v165+v166+v167+v168+v169+v170;
+ sum +=v171+v172+v173+v174+v175+v176+v177+v178+v179+v180;
+ sum +=v181+v182+v183+v184+v185+v186+v187+v188+v189+v190;
+ sum +=v191+v192+v193+v194+v195+v196+v197+v198+v199+v200;
+ sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210;
+ sum +=v211+v212+v213+v214+v215+v216+v217+v218+v219+v220;
+ sum +=v231+v232+v233+v234+v235+v236+v237+v238+v239+v240;
+ sum +=v241+v242+v243+v244+v245+v246+v247+v248+v249+v250;
+ sum +=v251+v252+v253+v254+v255+v256+v257+v258+v259+v260;
+ sum +=v261+v262+v263+v264+v265+v266+v267+v268+v269+v270;
+ sum +=v271+v272+v273+v274+v275+v276+v277+v278+v279+v280;
+ sum +=v281+v282+v283+v284+v285+v286+v287+v288+v289+v290;
+ sum +=v291+v292+v293+v294+v295+v296+v297+v298+v299+v300;
+
+ sum_after = sum;
+ }
+
+ return sum_before != sum_after;
+}
--
Andreas Schwab, SuSE Labs, schwab@suse.de
SuSE Linux Products GmbH, Maxfeldstraße 5, 90409 Nürnberg, Germany
PGP key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5
"And now for something completely different."