Index: gcc.fsf.bigconst/gcc/testsuite/gcc.dg/20060801-1.c
===================================================================
--- gcc.fsf.bigconst/gcc/testsuite/gcc.dg/20060801-1.c	(revision 0)
+++ gcc.fsf.bigconst/gcc/testsuite/gcc.dg/20060801-1.c	(revision 0)
@@ -0,0 +1,9 @@
+/* { dg-do compile { target { lp64 } } */
+/* { dg-options "-fPIC" } */
+char *ptr = 0;
+char array[100];
+void
+f()
+{
+  ptr = &array[0x100000000ULL];	/* A 33-bit constant.  */
+}
Index: gcc.fsf.bigconst/gcc/rtl.h
===================================================================
--- gcc.fsf.bigconst/gcc/rtl.h	(revision 115759)
+++ gcc.fsf.bigconst/gcc/rtl.h	(working copy)
@@ -996,6 +996,7 @@
 
 /* For a CONST_INT rtx, INTVAL extracts the integer.  */
 #define INTVAL(RTX) XCWINT(RTX, 0, CONST_INT)
+#define UINTVAL(RTX) ((unsigned HOST_WIDE_INT) INTVAL (RTX))
 
 /* For a CONST_DOUBLE:
    For a VOIDmode, there are two integers CONST_DOUBLE_LOW is the
Index: gcc.fsf.bigconst/gcc/config/rs6000/rs6000.c
===================================================================
--- gcc.fsf.bigconst/gcc/config/rs6000/rs6000.c	(revision 115759)
+++ gcc.fsf.bigconst/gcc/config/rs6000/rs6000.c	(working copy)
@@ -18105,7 +18105,7 @@
    position-independent addresses go into a reg.  This is REG if non
    zero, otherwise we allocate register(s) as necessary.  */
 
-#define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
+#define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
 
 rtx
 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,