This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: RFA: autoincrement patches for gcc 4 - updated patch


Joern RENNECKE <joern.rennecke@st.com> writes:

> >However, it seems to me that we can view this as two separate
> >optimizations.  The first one is to change the first code above into
> >this:
> >
> >    r1 = r0 + 8
> >    r2 = (r1)
> >    r1 = r1 + 4
> >    r4 = (r1)
> >
> >On machines without register offset addressing and with relatively few
> >registers, this is a useful optimization because it decreases register
> >pressure.
> 
> The code does that too, but only if the number of instructions is not
> increased.

That is good to hear.  But I think it might be easier to understand if
it were written as two separate passes, one for this optimization, and
for the auto-increment detection, rather than one complex pass (which
is part of another complex pass).

> >Then the second optimization is to do a better job of recognizing when
> >we can use auto-increment addressing.  I know that Ken Zadeck has done
> >some work on this on dataflow-branch.
> >
> Flow doesn't reconize auto-increment opportunities where the related
> addresses
> are held in different registers.

Sure.  This is something to fix.  If you queue it up with changes like
the above, then I think it will be much easier to detect the
auto-increment opportunities.

> >The patch as it stands, although written in a general manner, seems
> >quite specific to a very small number of processors: those without
> >register offset addressing but with auto-increment addressing.  I
> >suspect that FSF gcc supports exactly one processor with that
> >description.
> >
> Note that the addressing modes that are available depend not only on
> the processor,
> but also on the mode of the addressed item - or more general, on the
> instruction and
> the way the value is used in the instruction.

I believe that my point stands.

> >I've been able to run the gcc testsuite on
> >the ARM simulator before, so I know it is possible.
> >
> IIRC I tested the code on an arm simulator already.

Good.  I didn't see that in the threads I looked through.

Ian


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]