Re: PATCH: x86/x86-64: Support Intel MNI intrinsics

[Ian Lance Taylor <iant at google dot com>]

"H. J. Lu" <hjl@lucon.org> writes:

> On Fri, Jun 23, 2006 at 11:42:11AM -0700, Mike Stump wrote:
> > On Feb 24, 2006, at 12:47 PM, H. J. Lu wrote:
> > >These 2 patches implement Intel MNI intrinsics
> > 
> > These should all have __always_inline__ on them...
> 
> Here is the updated patch. I couldn't find published MNI spec. But
> anyone who has a Merom/Conroe/Woodcrest SDV should have access to
> MNI spec.

This patch looks generally OK to me, although I haven't read anything
about how the instructions work..  However, I am concerned about the
name Merom and the acronym MNI.  I'd rather get this right from the
start.  I did a few searches on the Intel web site.  I found this:
    http://www.intel.com/cd/ids/developer/asmo-na/eng/newsletter/286721.htm
which says "Get the much-awaited support for Intel.AN. Core$(C"b(B2 Duo
(formerly code named Merom) new instructions in processors with
Eclipse for Itanium.AN. 2 processor support and Cluster OpenMP*."  So
Merom is a code name, and we know that Intel doesn't keep those code
names going forward.  Do we really want to look in this option name?

Searching around in general, I see that some people are calling these
instructions SSE4.  E.g.,
    http://en.wikipedia.org/wiki/SSE4

Would it be possible to pin down the option name now so that we don't
have to change it in the future, and so that we don't have a backward
compatibilty problem?

Also, why are _mm_alignr_epi8 and _mm_alignr_pi8 implemented as macros
rather than inline functions?

Thanks.

Ian