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Re: [patch] MIPS V2SF RTL patterns
- From: Richard Sandiford <richard at codesourcery dot com>
- To: "Fu, Chao-Ying" <fu at mips dot com>
- Cc: <gcc-patches at gcc dot gnu dot org>, "Thekkath, Radhika" <radhika at mips dot com>
- Date: Tue, 09 May 2006 08:57:07 +0100
- Subject: Re: [patch] MIPS V2SF RTL patterns
- References: <3CB54817FDF733459B230DD27C690CEC012BB091@Exchange.mips.com>
"Fu, Chao-Ying" <fu@mips.com> writes:
> Hi Richard,
>
> Your patch looks good. Thanks a lot!
Thanks, now committed.
> Unlike 8 separate FCC registers, the MIPS32 DSP uses
> 4 bits in a DSP control register for comparison results.
> It may be a problem to deal with the single register scheme by
> using a vector of BI mode, I guess.
Sorry, I'm not sure I follow. Why couldn't the ccond field of the DSP
control register be treated as a vector of BI mode? I don't really
see how it's different from the fcc field of FCSR. (That's a genuine
question, in case it doesn't read like one. I think I'm missing
something here.)
Richard