This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
[csl-arm] Thumb-2 integer division instructions
- From: Paul Brook <paul at codesourcery dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Tue, 21 Mar 2006 14:59:32 +0000
- Subject: [csl-arm] Thumb-2 integer division instructions
The patch below makes gcc generate Thumb-2 integer division instructions when
available.
Tested with cross to arm-none-eabi.
Applied to csl-arm-branch.
Paul
2005-03-21 Paul Brook <paul@codesourcery.com>
* config/arm/thumb2.md (divsi3, udivsi3): New define_insn.
* config/arm/arm.c (arm_arch_hwdiv): Define.
(arm_override_options): Set arm_arch_hwdiv.
* config/arm/arm.h (arm_arch_hwdiv): Declare.
Index: gcc/config/arm/thumb2.md
===================================================================
--- gcc/config/arm/thumb2.md (revision 112231)
+++ gcc/config/arm/thumb2.md (working copy)
@@ -1090,3 +1090,23 @@ (define_insn "*thumb2_addsi_shortim"
[(set_attr "predicable" "yes")
(set_attr "length" "2")]
)
+
+(define_insn "divsi3"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (div:SI (match_operand:SI 1 "s_register_operand" "r")
+ (match_operand:SI 2 "s_register_operand" "r")))]
+ "TARGET_THUMB2 && arm_arch_hwdiv"
+ "sdiv%?\t%0, %1, %2"
+ [(set_attr "predicable" "yes")
+ (set_attr "length" "2")]
+)
+
+(define_insn "udivsi3"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (udiv:SI (match_operand:SI 1 "s_register_operand" "r")
+ (match_operand:SI 2 "s_register_operand" "r")))]
+ "TARGET_THUMB2 && arm_arch_hwdiv"
+ "udiv%?\t%0, %1, %2"
+ [(set_attr "predicable" "yes")
+ (set_attr "length" "2")]
+)
Index: gcc/config/arm/arm.c
===================================================================
--- gcc/config/arm/arm.c (revision 112231)
+++ gcc/config/arm/arm.c (working copy)
@@ -543,6 +543,9 @@ int arm_cpp_interwork = 0;
/* Nonzero if chip supports Thumb 2. */
int arm_arch_thumb2;
+/* Nonzero if chip supports integer division instruction. */
+int arm_arch_hwdiv;
+
/* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
must report the mode of the memory reference from PRINT_OPERAND to
PRINT_OPERAND_ADDRESS. */
@@ -1160,6 +1163,7 @@ arm_override_options (void)
arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
+ arm_arch_hwdiv = (insn_flags & FL_DIV) != 0;
/* V5 code we generate is completely interworking capable, so we turn off
TARGET_INTERWORK here to avoid many tests later on. */
Index: gcc/config/arm/arm.h
===================================================================
--- gcc/config/arm/arm.h (revision 112231)
+++ gcc/config/arm/arm.h (working copy)
@@ -378,6 +378,9 @@ extern int arm_cpp_interwork;
/* Nonzero if chip supports Thumb 2. */
extern int arm_arch_thumb2;
+/* Nonzero if chip supports integer division instruction. */
+extern int arm_arch_hwdiv;
+
#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_APCS_FRAME)
#endif