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Re: [PATCH] PR 26276
- From: Kazuhiro Inaoka <inaoka dot kazuhiro at renesas dot com>
- To: Nick Clifton <nickc at redhat dot com>
- Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Date: Tue, 21 Mar 2006 21:43:34 +0900
- Subject: Re: [PATCH] PR 26276
- References: <43F1A962.8000809@renesas.com> <43F4BCF4.3070702@redhat.com>
Long time Nick,
Remake a ChangeLog and patches.
Checked by testsuite in gcc-3.4-branch, gcc-4.0-branch.
There were no regretions. (PASSED 20040123-1.c)
Regards,
Kazuhiro Inaoka
Nick Clifton wrote:
Hi Kazuhiro,
These are patches for PR 26276.
Please commit into gcc-3.4-branch, gcc-4.0-branch and mainline.
Sorry no - this patch needs tidying up. Specifically:
* Please describe what is being changed in the ChangeLog entry,
rather than just saying that a PR is being fixed. Also please
put the PR number on a line by itself at the start of the entry.
There are several examples of this in other entries in the
ChangeLog.
* Please remove the #if 0... #endif sequences from the patch.
Suppressed code like this should just be removed, and instead
you can add a comment explaining why unsigned operations are
being used rather than signed operations.
* When you do add comments, please follow the GNU Coding Standard
for them. ie /* This. */ rather than
/*
* This.
*/
Please also report how you tested the patch and whether there were any
regressions or improvements when you ran the GCC testsuite.
Cheers
Nick
2006-03-21 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
PR target/36276
* config/m32r/m32r.c (gen_compare): Removed a rule addsi3 codes
to avoid a miss optimizing at simplify_relational_operation().
* config/m32r/m32r.md (seq): Ditto. Changed reg_or_eq_int16_operand
to reg_or_uint16_operand because seq_insn has not used addsi3 already.
(seq_insn): Ditto. Removed operand check mode "P". Changed
reg_or_eq_int16_operand to reg_or_uint16_operand.
Index: m32r.c
===================================================================
--- m32r.c (revision 109855)
+++ m32r.c (working copy)
@@ -1028,12 +1028,12 @@
{
case EQ:
if (GET_CODE (y) == CONST_INT
- && CMP_INT16_P (INTVAL (y)) /* Reg equal to small const. */
+ && UINT16_P (INTVAL (y)) /* Reg equal to small const. */
&& y != const0_rtx)
{
rtx tmp = gen_reg_rtx (SImode);
- emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
+ emit_insn (gen_xorsi3 (tmp, x, GEN_INT (INTVAL (y))));
x = tmp;
y = const0_rtx;
}
@@ -1151,11 +1151,11 @@
/* Reg/smallconst equal comparison. */
if (compare_code == EQ
&& GET_CODE (y) == CONST_INT
- && CMP_INT16_P (INTVAL (y)))
+ && UINT16_P (INTVAL (y)))
{
rtx tmp = gen_reg_rtx (SImode);
- emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
+ emit_insn (gen_xorsi3 (tmp, x, GEN_INT (INTVAL (y))));
return gen_rtx (code, CCmode, tmp, const0_rtx);
}
Index: m32r.md
===================================================================
--- m32r.md (revision 109855)
+++ m32r.md (working copy)
@@ -1690,7 +1691,7 @@
DONE;
}
- if (! reg_or_eq_int16_operand (op2, mode))
+ if (! reg_or_uint16_operand (op2, mode))
op2 = force_reg (mode, op2);
emit_insn (gen_seq_insn (op0, op1, op2));
@@ -1752,7 +1753,7 @@
(define_insn "seq_insn"
[(set (match_operand:SI 0 "register_operand" "=r,r,??r,r")
(eq:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_eq_int16_operand" "r,r,r,PK")))
+ (match_operand:SI 2 "reg_or_uint16_operand" "r,r,r,K")))
(clobber (reg:CC 17))
(clobber (match_scratch:SI 3 "=1,2,&r,r"))]
"TARGET_M32R"
@@ -1763,7 +1764,7 @@
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(eq:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "reg_or_eq_int16_operand" "")))
+ (match_operand:SI 2 "reg_or_uint16_operand" "")))
(clobber (reg:CC 17))
(clobber (match_scratch:SI 3 ""))]
"TARGET_M32R && reload_completed"
@@ -1791,11 +1792,7 @@
op1 = op3;
}
- if (GET_CODE (op2) == CONST_INT && (value = INTVAL (op2)) != 0
- && CMP_INT16_P (value))
- emit_insn (gen_addsi3 (op3, op1, GEN_INT (-value)));
- else
- emit_insn (gen_xorsi3 (op3, op1, op2));
+ emit_insn (gen_xorsi3 (op3, op1, op2));
emit_insn (gen_cmp_ltusi_insn (op3, GEN_INT (1)));
emit_insn (gen_movcc_insn (op0));
Index: m32r.c
===================================================================
--- m32r.c (revision 111172)
+++ m32r.c (working copy)
@@ -1031,12 +1031,11 @@
{
case EQ:
if (GET_CODE (y) == CONST_INT
- && CMP_INT16_P (INTVAL (y)) /* Reg equal to small const. */
- && y != const0_rtx)
+ && UINT16_P (INTVAL (y)))
{
rtx tmp = gen_reg_rtx (SImode);
- emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
+ emit_insn (gen_xorsi3 (tmp, x, GEN_INT (INTVAL (y))));
x = tmp;
y = const0_rtx;
}
@@ -1154,11 +1153,11 @@
/* Reg/smallconst equal comparison. */
if (compare_code == EQ
&& GET_CODE (y) == CONST_INT
- && CMP_INT16_P (INTVAL (y)))
+ && UINT16_P (INTVAL (y)))
{
rtx tmp = gen_reg_rtx (SImode);
- emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
+ emit_insn (gen_xorsi3 (tmp, x, GEN_INT (INTVAL (y))));
return gen_rtx_fmt_ee (code, CCmode, tmp, const0_rtx);
}
Index: m32r.md
===================================================================
--- m32r.md (revision 111172)
+++ m32r.md (working copy)
@@ -1609,7 +1609,7 @@
DONE;
}
- if (! reg_or_eq_int16_operand (op2, mode))
+ if (! reg_or_uint16_operand (op2, mode))
op2 = force_reg (mode, op2);
emit_insn (gen_seq_insn (op0, op1, op2));
@@ -1671,7 +1671,7 @@
(define_insn "seq_insn"
[(set (match_operand:SI 0 "register_operand" "=r,r,??r,r")
(eq:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_eq_int16_operand" "r,r,r,PK")))
+ (match_operand:SI 2 "reg_or_uint16_operand" "r,r,r,K")))
(clobber (reg:CC 17))
(clobber (match_scratch:SI 3 "=1,2,&r,r"))]
"TARGET_M32R"
@@ -1682,7 +1682,7 @@
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(eq:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "reg_or_eq_int16_operand" "")))
+ (match_operand:SI 2 "reg_or_uint16_operand" "")))
(clobber (reg:CC 17))
(clobber (match_scratch:SI 3 ""))]
"TARGET_M32R && reload_completed"
@@ -1710,11 +1710,7 @@
op1 = op3;
}
- if (GET_CODE (op2) == CONST_INT && (value = INTVAL (op2)) != 0
- && CMP_INT16_P (value))
- emit_insn (gen_addsi3 (op3, op1, GEN_INT (-value)));
- else
- emit_insn (gen_xorsi3 (op3, op1, op2));
+ emit_insn (gen_xorsi3 (op3, op1, op2));
emit_insn (gen_cmp_ltusi_insn (op3, const1_rtx));
emit_insn (gen_movcc_insn (op0));