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[patch] Arm PLD instruction
- From: Paul Brook <paul at codesourcery dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Tue, 21 Feb 2006 21:46:30 +0000
- Subject: [patch] Arm PLD instruction
The attached patch fixes two bugs in assembly of the Arm PLD instruction.
The arm routine was incorrectly adding the wrong register value to the opcode
(this is done by encode_arm_addr_mode_2). The Thumb routine was looking at
the wrong operand.
Tested with cross to arm-none-eabi.
Ok?
Paul
2005-02-21 Paul Brook <paul@codesourcery.com>
gas/
* config/tc-arm.c (do_pld): Remove incorrect write to
inst.instruction.
(encode_thumb32_addr_mode): Use correct operand.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected pld opcode.
Index: gas/config/tc-arm.c
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/config/tc-arm.c,v
retrieving revision 1.240
diff -u -p -r1.240 tc-arm.c
--- gas/config/tc-arm.c 2 Feb 2006 20:19:56 -0000 1.240
+++ gas/config/tc-arm.c 21 Feb 2006 21:02:00 -0000
@@ -5181,7 +5232,6 @@ do_pld (void)
_("writeback used in preload instruction"));
constraint (!inst.operands[0].preind,
_("unindexed addressing used in preload instruction"));
- inst.instruction |= inst.operands[0].reg;
encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
}
@@ -5900,7 +5966,7 @@ encode_thumb32_addr_mode (int i, bfd_boo
constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
_("Thumb supports only LSL in shifted register indexing"));
- inst.instruction |= inst.operands[1].imm;
+ inst.instruction |= inst.operands[i].imm;
if (inst.operands[i].shifted)
{
constraint (inst.reloc.exp.X_op != O_constant,
@@ -5916,7 +5982,7 @@ encode_thumb32_addr_mode (int i, bfd_boo
{
constraint (is_pc && inst.operands[i].writeback,
_("cannot use writeback with PC-relative addressing"));
- constraint (is_t && inst.operands[1].writeback,
+ constraint (is_t && inst.operands[i].writeback,
_("cannot use writeback with this instruction"));
if (is_d)
Index: gas/testsuite/gas/arm/thumb32.d
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/testsuite/gas/arm/thumb32.d,v
retrieving revision 1.13
diff -u -p -r1.13 thumb32.d
--- gas/testsuite/gas/arm/thumb32.d 8 Sep 2005 12:49:25 -0000 1.13
+++ gas/testsuite/gas/arm/thumb32.d 21 Feb 2006 20:59:10 -0000
@@ -513,8 +513,8 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f815 f930 pld \[r5\], #-48
0[0-9a-f]+ <[^>]+> f815 ff30 pld \[r5, #48\]!
0[0-9a-f]+ <[^>]+> f815 fd30 pld \[r5, #-48\]!
-0[0-9a-f]+ <[^>]+> f815 f000 pld \[r5, r0\]
-0[0-9a-f]+ <[^>]+> f819 f000 pld \[r9, r0\]
+0[0-9a-f]+ <[^>]+> f815 f004 pld \[r5, r4\]
+0[0-9a-f]+ <[^>]+> f819 f00c pld \[r9, ip\]
0[0-9a-f]+ <[^>]+> f89f f006 pld \[pc, #6\] ; 0+5ba <[^>]+>
0[0-9a-f]+ <[^>]+> f81f f02a pld \[pc, #-42\] ; 0+58e <[^>]+>
0[0-9a-f]+ <[^>]+> e9d5 2300 ldrd r2, r3, \[r5\]