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[PATCH] PR 26276

From: Kazuhiro Inaoka <inaoka dot kazuhiro at renesas dot com>
To: Nick Clifton <nickc at redhat dot com>
Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
Date: Tue, 14 Feb 2006 18:56:50 +0900
Subject: [PATCH] PR 26276

Hi Nick,

These are patches for PR 26276.

Please commit into gcc-3.4-branch, gcc-4.0-branch and mainline.

Regards,
Kazuhiro Inaoka
EC No. H05-0044

gcc/ChangeLog

2005-02-14 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>

* config/m32r/m32r.c (gen_compare): Fixed PR 26276. * config/m32r/m32r.md (seq) : Ditto. (seq_insn): Ditto.

Index: m32r.c
===================================================================
--- m32r.c	(revision 109855)
+++ m32r.c	(working copy)
@@ -1028,6 +1028,20 @@
 	{
 	case EQ:
 	  if (GET_CODE (y) == CONST_INT
+	      && UINT16_P (INTVAL (y))		/* Reg equal to small const.  */
+	      && y != const0_rtx)
+	    {
+	      rtx tmp = gen_reg_rtx (SImode);		
+	      
+	      emit_insn (gen_xorsi3 (tmp, x, GEN_INT (INTVAL (y))));
+	      x = tmp;
+	      y = const0_rtx;
+	    }
+#if 0
+ /*
+  * Removed for miss optimizing at simplify_relational_operation().
+  */
+	  else if (GET_CODE (y) == CONST_INT
 	      && CMP_INT16_P (INTVAL (y))		/* Reg equal to small const.  */
 	      && y != const0_rtx)
 	    {
@@ -1037,6 +1051,7 @@
 	      x = tmp;
 	      y = const0_rtx;
 	    }
+#endif
 	  else if (CONSTANT_P (y))			/* Reg equal to const.  */
 	    {
 	      rtx tmp = force_reg (GET_MODE (x), y);
@@ -1151,6 +1166,20 @@
       /* Reg/smallconst equal comparison.  */
       if (compare_code == EQ
 	  && GET_CODE (y) == CONST_INT
+	  && UINT16_P (INTVAL (y)))
+	{
+	  rtx tmp = gen_reg_rtx (SImode);
+
+	  emit_insn (gen_xorsi3 (tmp, x, GEN_INT (INTVAL (y))));
+	  return gen_rtx (code, CCmode, tmp, const0_rtx);
+	}
+      
+#if 0
+ /*
+  * Removed for miss optimizing at simplify_relational_operation().
+  */
+      if (compare_code == EQ
+	  && GET_CODE (y) == CONST_INT
 	  && CMP_INT16_P (INTVAL (y)))
 	{
 	  rtx tmp = gen_reg_rtx (SImode);
@@ -1158,6 +1187,7 @@
 	  emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
 	  return gen_rtx (code, CCmode, tmp, const0_rtx);
 	}
+#endif
       
       /* Reg/const equal comparison.  */
       if (compare_code == EQ
Index: m32r.md
===================================================================
--- m32r.md	(revision 109855)
+++ m32r.md	(working copy)
@@ -1690,7 +1691,7 @@
       DONE;
     }
 
-  if (! reg_or_eq_int16_operand (op2, mode))
+  if (! reg_or_uint16_operand (op2, mode))
     op2 = force_reg (mode, op2);
 
   emit_insn (gen_seq_insn (op0, op1, op2));
@@ -1752,7 +1753,7 @@
 (define_insn "seq_insn"
   [(set (match_operand:SI 0 "register_operand" "=r,r,??r,r")
 	(eq:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
-	       (match_operand:SI 2 "reg_or_eq_int16_operand" "r,r,r,PK")))
+	       (match_operand:SI 2 "reg_or_uint16_operand" "r,r,r,K")))
    (clobber (reg:CC 17))
    (clobber (match_scratch:SI 3 "=1,2,&r,r"))]
   "TARGET_M32R"
@@ -1763,7 +1764,7 @@
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
 	(eq:SI (match_operand:SI 1 "register_operand" "")
-	       (match_operand:SI 2 "reg_or_eq_int16_operand" "")))
+	       (match_operand:SI 2 "reg_or_uint16_operand" "")))
    (clobber (reg:CC 17))
    (clobber (match_scratch:SI 3 ""))]
   "TARGET_M32R && reload_completed"
@@ -1791,10 +1792,14 @@
       op1 = op3;
     }
 
-  if (GET_CODE (op2) == CONST_INT && (value = INTVAL (op2)) != 0
-      && CMP_INT16_P (value))
-    emit_insn (gen_addsi3 (op3, op1, GEN_INT (-value)));
-  else
+/*
+ * Removed for miss optimizing at simplify_relational_operation().
+ *
+ *  if (GET_CODE (op2) == CONST_INT && (value = INTVAL (op2)) != 0
+ *      && CMP_INT16_P (value))
+ *    emit_insn (gen_addsi3 (op3, op1, GEN_INT (-value)));
+ *  else
+ */
     emit_insn (gen_xorsi3 (op3, op1, op2));
 
   emit_insn (gen_cmp_ltusi_insn (op3, GEN_INT (1)));

Index: m32r.c
===================================================================
--- m32r.c	(revision 109869)
+++ m32r.c	(working copy)
@@ -1031,6 +1031,19 @@
 	{
 	case EQ:
 	  if (GET_CODE (y) == CONST_INT
+	      && UINT16_P (INTVAL (y)))
+	    {
+	      rtx tmp = gen_reg_rtx (SImode);		
+	      
+	      emit_insn (gen_xorsi3 (tmp, x, GEN_INT (INTVAL (y))));
+	      x = tmp;
+	      y = const0_rtx;
+	    }
+#if 0
+  /*
+   * Removed for miss optimizing at simplify_relational_operation().
+   */
+	  else if (GET_CODE (y) == CONST_INT
 	      && CMP_INT16_P (INTVAL (y))		/* Reg equal to small const.  */
 	      && y != const0_rtx)
 	    {
@@ -1040,6 +1053,7 @@
 	      x = tmp;
 	      y = const0_rtx;
 	    }
+#endif
 	  else if (CONSTANT_P (y))			/* Reg equal to const.  */
 	    {
 	      rtx tmp = force_reg (GET_MODE (x), y);
@@ -1154,6 +1168,20 @@
       /* Reg/smallconst equal comparison.  */
       if (compare_code == EQ
 	  && GET_CODE (y) == CONST_INT
+	  && UINT16_P (INTVAL (y)))
+	{
+	  rtx tmp = gen_reg_rtx (SImode);
+
+	  emit_insn (gen_xorsi3 (tmp, x, GEN_INT (INTVAL (y))));
+	  return gen_rtx_fmt_ee (code, CCmode, tmp, const0_rtx);
+	}
+      
+#if 0
+  /*
+   * Removed for miss optimizing at simplify_relational_operation().
+   */
+      if (compare_code == EQ
+	  && GET_CODE (y) == CONST_INT
 	  && CMP_INT16_P (INTVAL (y)))
 	{
 	  rtx tmp = gen_reg_rtx (SImode);
@@ -1161,6 +1189,7 @@
 	  emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
 	  return gen_rtx_fmt_ee (code, CCmode, tmp, const0_rtx);
 	}
+#endif
       
       /* Reg/const equal comparison.  */
       if (compare_code == EQ
Index: m32r.md
===================================================================
--- m32r.md	(revision 109869)
+++ m32r.md	(working copy)
@@ -1609,7 +1609,7 @@
       DONE;
     }
 
-  if (! reg_or_eq_int16_operand (op2, mode))
+  if (! reg_or_uint16_operand (op2, mode))
     op2 = force_reg (mode, op2);
 
   emit_insn (gen_seq_insn (op0, op1, op2));
@@ -1671,7 +1671,7 @@
 (define_insn "seq_insn"
   [(set (match_operand:SI 0 "register_operand" "=r,r,??r,r")
 	(eq:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
-	       (match_operand:SI 2 "reg_or_eq_int16_operand" "r,r,r,PK")))
+	       (match_operand:SI 2 "reg_or_uint16_operand" "r,r,r,K")))
    (clobber (reg:CC 17))
    (clobber (match_scratch:SI 3 "=1,2,&r,r"))]
   "TARGET_M32R"
@@ -1682,7 +1682,7 @@
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
 	(eq:SI (match_operand:SI 1 "register_operand" "")
-	       (match_operand:SI 2 "reg_or_eq_int16_operand" "")))
+	       (match_operand:SI 2 "reg_or_uint16_operand" "")))
    (clobber (reg:CC 17))
    (clobber (match_scratch:SI 3 ""))]
   "TARGET_M32R && reload_completed"
@@ -1710,10 +1710,14 @@
       op1 = op3;
     }
 
-  if (GET_CODE (op2) == CONST_INT && (value = INTVAL (op2)) != 0
-      && CMP_INT16_P (value))
-    emit_insn (gen_addsi3 (op3, op1, GEN_INT (-value)));
-  else
+/* 
+ * Removed for miss optimizing at simplify_relational_operation().
+ *
+ *  if (GET_CODE (op2) == CONST_INT && (value = INTVAL (op2)) != 0
+ *      && CMP_INT16_P (value))
+ *    emit_insn (gen_addsi3 (op3, op1, GEN_INT (-value)));
+ *  else
+ */
     emit_insn (gen_xorsi3 (op3, op1, op2));
 
   emit_insn (gen_cmp_ltusi_insn (op3, const1_rtx));

Follow-Ups:
- Re: [PATCH] PR 26276
  - From: Nick Clifton

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