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*smax_m1 for ARM
- From: Nicolas Pitre <nico at cam dot org>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Richard Earnshaw <rearnsha at arm dot com>
- Date: Tue, 31 Jan 2006 12:36:25 -0500 (EST)
- Subject: *smax_m1 for ARM
- References: <Pine.LNX.4.64.0601241302550.16649@localhost.localdomain> <1138185066.26919.17.camel@pc960.cambridge.arm.com> <Pine.LNX.4.64.0601261525220.16649@localhost.localdomain> <1138633286.2396.7.camel@pc960.cambridge.arm.com> <Pine.LNX.4.64.0601301040390.16649@localhost.localdomain> <1138717824.22799.0.camel@pc960.cambridge.arm.com>
I just committed the patch below acked by Richard Earnshaw, heavily
copied on Richard's earlier *smax_0 patch.
It was tested with trivial test runs, plus extensive inspection of
generated assembly for various piece of code containing "if (x<0) x = -1"
sequences.
2006-01-31 Nicolas Pitre <nico@cam.org>
* arm.md (smaxsi3): Make aware of smax_m1.
(smax_m1): New.
Index: config/arm/arm.md
===================================================================
--- config/arm/arm.md (revision 110442)
+++ config/arm/arm.md (working copy)
@@ -2481,7 +2481,7 @@
(clobber (reg:CC CC_REGNUM))])]
"TARGET_ARM"
"
- if (operands[2] == const0_rtx)
+ if (operands[2] == const0_rtx || operands[2] == constm1_rtx)
{
/* No need for a clobber of the condition code register here. */
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
@@ -2500,6 +2500,15 @@
[(set_attr "predicable" "yes")]
)
+(define_insn "*smax_m1"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (smax:SI (match_operand:SI 1 "s_register_operand" "r")
+ (const_int -1)))]
+ "TARGET_ARM"
+ "orr%?\\t%0, %1, %1, asr #31"
+ [(set_attr "predicable" "yes")]
+)
+
(define_insn "*smax_insn"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(smax:SI (match_operand:SI 1 "s_register_operand" "%0,?r")
Nicolas