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[patch] S/390: cleanup machine description (2/3)
- From: Adrian Straetling <straetling at de dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: "Weigand, Ulrich" <uweigand at de dot ibm dot com>
- Date: Wed, 14 Dec 2005 13:31:21 +0100
- Subject: [patch] S/390: cleanup machine description (2/3)
- References: <20051214122057.GA14449@de.ibm.com>
On Wed, Dec 14, 2005 at 01:20:57PM +0100, Adrian Straetling wrote:
> Hi,
>
> this little series of patches performs some cleanup that is waiting on
> my disk for some time now.
>
> All bootstrap fine and regtest without regressions.
this second patch merges many sign and zero extension patterns.
Ok for 4.2?
2005-12-14 Adrian Straetling <straetling@de.ibm.com>
* gcc/config/s390/s390.md ("extend<mode>di2","extend<mode>si2"): Merge.
("*extendqidi2_extimm","*extendqisi2_extimm"): Merge.
("*extendqidi2","*extendqisi2") Merge.
("*extendqidi2_short_displ","*extendqisi2_short_displ"): Merge.
("zero_extendhidi2","zero_extendqidi2"): Merge.
("*zero_extend<mode>di2_extimm","*zero_extend<mode>si2_extimm"): Merge.
Move some pattern to retain partial ordering.
Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig 2005-12-13 11:58:25.000000000 +0100
--- gcc/config/s390/s390.md 2005-12-13 12:36:55.796521831 +0100
*************** (define_insn "*extendsidi2"
*** 2692,2723 ****
[(set_attr "op_type" "RRE,RXY")])
;
! ; extend(hi|qi)di2 instruction pattern(s).
;
! (define_expand "extend<mode>di2"
! [(set (match_operand:DI 0 "register_operand" "")
! (sign_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
""
{
! if (!TARGET_64BIT)
{
rtx tmp = gen_reg_rtx (SImode);
! emit_insn (gen_extend<mode>si2 (tmp, operands[1]));
emit_insn (gen_extendsidi2 (operands[0], tmp));
DONE;
}
else if (!TARGET_EXTIMM)
{
! rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) -
! GET_MODE_BITSIZE (<MODE>mode));
! operands[1] = gen_lowpart (DImode, operands[1]);
! emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
! emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount));
DONE;
}
})
(define_insn "*extendhidi2_extimm"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
--- 2692,2728 ----
[(set_attr "op_type" "RRE,RXY")])
;
! ; extend(hi|qi)(si|di)2 instruction pattern(s).
;
! (define_expand "extend<HQI:mode><DSI:mode>2"
! [(set (match_operand:DSI 0 "register_operand" "")
! (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
""
{
! if (<DSI:MODE>mode == DImode && !TARGET_64BIT)
{
rtx tmp = gen_reg_rtx (SImode);
! emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
emit_insn (gen_extendsidi2 (operands[0], tmp));
DONE;
}
else if (!TARGET_EXTIMM)
{
! rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
! GET_MODE_BITSIZE (<HQI:MODE>mode));
!
! operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
! emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
! emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
DONE;
}
})
+ ;
+ ; extendhidi2 instruction pattern(s).
+ ;
+
(define_insn "*extendhidi2_extimm"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
*************** (define_insn "*extendhidi2"
*** 2734,2793 ****
"lgh\t%0,%1"
[(set_attr "op_type" "RXY")])
- (define_insn "*extendqidi2_extimm"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
- "TARGET_64BIT && TARGET_EXTIMM"
- "@
- lgbr\t%0,%1
- lgb\t%0,%1"
- [(set_attr "op_type" "RRE,RXY")])
-
- (define_insn "*extendqidi2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
- "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
- "lgb\t%0,%1"
- [(set_attr "op_type" "RXY")])
-
- (define_insn_and_split "*extendqidi2_short_displ"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
- "#"
- "&& reload_completed"
- [(parallel
- [(set (match_dup 0) (unspec:DI [(match_dup 1) (const_int 8)] UNSPEC_ICM))
- (clobber (reg:CC CC_REGNUM))])
- (parallel
- [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
- (clobber (reg:CC CC_REGNUM))])]
- {
- operands[1] = adjust_address (operands[1], BLKmode, 0);
- set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
- })
-
;
! ; extend(hi|qi)si2 instruction pattern(s).
;
- (define_expand "extend<mode>si2"
- [(set (match_operand:SI 0 "register_operand" "")
- (sign_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
- ""
- {
- if (!TARGET_EXTIMM)
- {
- rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) -
- GET_MODE_BITSIZE(<MODE>mode));
- operands[1] = gen_lowpart (SImode, operands[1]);
- emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount));
- emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount));
- DONE;
- }
- })
-
(define_insn "*extendhisi2_extimm"
[(set (match_operand:SI 0 "register_operand" "=d,d,d")
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))]
--- 2739,2748 ----
"lgh\t%0,%1"
[(set_attr "op_type" "RXY")])
;
! ; extendhisi2 instruction pattern(s).
;
(define_insn "*extendhisi2_extimm"
[(set (match_operand:SI 0 "register_operand" "=d,d,d")
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))]
*************** (define_insn "*extendhisi2"
*** 2807,2844 ****
lhy\t%0,%1"
[(set_attr "op_type" "RX,RXY")])
! (define_insn "*extendqisi2_extimm"
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
"TARGET_EXTIMM"
"@
! lbr\t%0,%1
! lb\t%0,%1"
[(set_attr "op_type" "RRE,RXY")])
! (define_insn "*extendqisi2"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
! "TARGET_LONG_DISPLACEMENT && !TARGET_EXTIMM"
! "lb\t%0,%1"
[(set_attr "op_type" "RXY")])
! (define_insn_and_split "*extendqisi2_short_displ"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
(clobber (reg:CC CC_REGNUM))]
! "!TARGET_LONG_DISPLACEMENT"
"#"
"&& reload_completed"
[(parallel
! [(set (match_dup 0) (unspec:SI [(match_dup 1) (const_int 8)] UNSPEC_ICM))
(clobber (reg:CC CC_REGNUM))])
(parallel
! [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
(clobber (reg:CC CC_REGNUM))])]
{
operands[1] = adjust_address (operands[1], BLKmode, 0);
set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
})
;
--- 2762,2805 ----
lhy\t%0,%1"
[(set_attr "op_type" "RX,RXY")])
! ;
! ; extendqi(si|di)2 instruction pattern(s).
! ;
!
! (define_insn "*extendqi<mode>2_extimm"
! [(set (match_operand:GPR 0 "register_operand" "=d,d")
! (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
"TARGET_EXTIMM"
"@
! l<g>br\t%0,%1
! l<g>b\t%0,%1"
[(set_attr "op_type" "RRE,RXY")])
! (define_insn "*extendqi<mode>2"
! [(set (match_operand:GPR 0 "register_operand" "=d")
! (sign_extend:GPR (match_operand:QI 1 "memory_operand" "m")))]
! "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
! "l<g>b\t%0,%1"
[(set_attr "op_type" "RXY")])
! (define_insn_and_split "*extendqi<mode>2_short_displ"
! [(set (match_operand:GPR 0 "register_operand" "=d")
! (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
(clobber (reg:CC CC_REGNUM))]
! "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
"#"
"&& reload_completed"
[(parallel
! [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
(clobber (reg:CC CC_REGNUM))])
(parallel
! [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
(clobber (reg:CC CC_REGNUM))])]
{
operands[1] = adjust_address (operands[1], BLKmode, 0);
set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
+ operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
+ - GET_MODE_BITSIZE (QImode));
})
;
*************** (define_insn "*zero_extendsidi2"
*** 2874,2922 ****
[(set_attr "op_type" "RRE,RXY")])
;
- ; zero_extend(hi|qi)di2 instruction pattern(s).
- ;
-
- (define_expand "zero_extend<mode>di2"
- [(set (match_operand:DI 0 "register_operand" "")
- (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
- ""
- {
- if (!TARGET_64BIT)
- {
- rtx tmp = gen_reg_rtx (SImode);
- emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
- emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
- DONE;
- }
- else if (!TARGET_EXTIMM)
- {
- rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
- GET_MODE_BITSIZE(<MODE>mode));
- operands[1] = gen_lowpart (DImode, operands[1]);
- emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
- emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
- DONE;
- }
- })
-
- (define_insn "*zero_extend<mode>di2_extimm"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
- "TARGET_64BIT && TARGET_EXTIMM"
- "@
- llg<hc>r\t%0,%1
- llg<hc>\t%0,%1"
- [(set_attr "op_type" "RRE,RXY")])
-
- (define_insn "*zero_extend<mode>di2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))]
- "TARGET_64BIT && !TARGET_EXTIMM"
- "llg<hc>\t%0,%1"
- [(set_attr "op_type" "RXY")])
-
- ;
; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
;
--- 2835,2840 ----
*************** (define_split
*** 2973,2981 ****
"")
;
! ; zero_extend(hi|qi)si2 instruction pattern(s).
;
(define_expand "zero_extend<mode>si2"
[(set (match_operand:SI 0 "register_operand" "")
(zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
--- 2891,2922 ----
"")
;
! ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
;
+ (define_expand "zero_extend<mode>di2"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
+ ""
+ {
+ if (!TARGET_64BIT)
+ {
+ rtx tmp = gen_reg_rtx (SImode);
+ emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
+ emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
+ DONE;
+ }
+ else if (!TARGET_EXTIMM)
+ {
+ rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
+ GET_MODE_BITSIZE(<MODE>mode));
+ operands[1] = gen_lowpart (DImode, operands[1]);
+ emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
+ emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
+ DONE;
+ }
+ })
+
(define_expand "zero_extend<mode>si2"
[(set (match_operand:SI 0 "register_operand" "")
(zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
*************** (define_expand "zero_extend<mode>si2"
*** 2987,3007 ****
emit_insn (gen_andsi3 (operands[0], operands[1],
GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
DONE;
! }
})
! (define_insn "*zero_extend<mode>si2_extimm"
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
"TARGET_EXTIMM"
"@
! ll<hc>r\t%0,%1
! ll<hc>\t%0,%1"
[(set_attr "op_type" "RRE,RXY")])
! (define_insn "*zero_extend<mode>si2_64"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))]
"TARGET_ZARCH && !TARGET_EXTIMM"
"llg<hc>\t%0,%1"
[(set_attr "op_type" "RXY")])
--- 2928,2948 ----
emit_insn (gen_andsi3 (operands[0], operands[1],
GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
DONE;
! }
})
! (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
! [(set (match_operand:GPR 0 "register_operand" "=d,d")
! (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
"TARGET_EXTIMM"
"@
! ll<g><hc>r\t%0,%1
! ll<g><hc>\t%0,%1"
[(set_attr "op_type" "RRE,RXY")])
! (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
! [(set (match_operand:GPR 0 "register_operand" "=d")
! (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "m")))]
"TARGET_ZARCH && !TARGET_EXTIMM"
"llg<hc>\t%0,%1"
[(set_attr "op_type" "RXY")])