Re: -fasm=intel not always suppported

[Andrew Pinski <pinskia at physics dot uc dot edu>]

> 
> > 
> > On Nov 15, 2005, at 11:50 AM, Andrew Pinski wrote:
> > > Yes support of intel style asm in GCC based inline-asm.
> > 
> > Not had any requests for that.
> 
> 
> Now you have.

Oh, that is because they did not know about the feature.  Hint hint.

And how many times did the FSF get a request for MS style inline-asm,
almost none.  If anyone uses inline-asm for more than like locks, instructions
which GCC cannot emit, they are asking for trouble.

GCC can emit SSE code (not that well but that is a different story and fixing
that would be the correct way of fixing the problem instead of using inline-asm).

Also x86 inline-asm is harder than what you put it.  It is not a matter of geting
the constraints right but a matter of saying which register gets clobbered and
which register gets placed where.

An example of this is rdtsc which takes no operands but places its result in 
eax:edx, how would you write that in MS style asm?
You would have to use an extra mov instruction like:

long long f(void)
{
  unsigned long a, b;
  asm
  {
    rdtsc
    mov a, eax
    mov b, ebx
  }

  return (a << 32ULL) | b;
}

what happens if you write it as:
long long f(void)
{
  asm { rdtsc }
  return 0;
}

Does your code mark eax and ebx as being clobbered if it does not, then there
is a bug and most likely other things like this.