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[PATCH, committed] Add POWER5+ FP rounding instructions
- From: David Edelsohn <dje at watson dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Tue, 15 Nov 2005 00:04:31 -0500
- Subject: [PATCH, committed] Add POWER5+ FP rounding instructions
This patch adds the optional PowerPC V2.02 FP rounding
instructions implemented in the POWER5+ processor. It also adds some
predefined macros for features.
Bootstrapped and regression tested on powerpc-ibm-aix5.2.0.0
David
* doc/invoke.texi (RS/6000 and PowerPC Options): Add -mmfcrf,
-mpopcntb, -mfprnd. Add -mcpu=power5+.
* configure.ac: Add test for FP rounding instructions.
* configure: Regenerate.
* config.in: Regenerate.
* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Define
_ARCH_PPCSQ, _ARCH_PPCGR, _ARCH_PWR4, _ARCH_PWR5, _ARCH_PWR5X if
features enabled.
* config/rs6000/rs6000.opt (mfprnd): New.
* config/rs6000/rs6000.c (processor_target_table): Add power5+.
(POWERPC_MASKS): Add MASK_POPCNTB and MASK_FPRND.
* config/rs6000/aix52.h (ASM_CPU_SPEC): Add -mpower5+.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Add -mpower5+.
(TARGET_FPRND): New.
* config/rs6000/rs6000.md (UNSPEC_FRIM, UNSPEC_FRIN, UNSPEC_FRIP,
UNSPEC_FRIZ): New.
(btrunc<mode>2): New.
(ceil<mode>2): New.
(floor<mode>2): New.
(round<mode>2): New.
Index: doc/invoke.texi
===================================================================
*** doc/invoke.texi (revision 106928)
--- doc/invoke.texi (working copy)
*************** See RS/6000 and PowerPC Options.
*** 636,641 ****
--- 636,642 ----
-maltivec -mno-altivec @gol
-mpowerpc-gpopt -mno-powerpc-gpopt @gol
-mpowerpc-gfxopt -mno-powerpc-gfxopt @gol
+ -mmfcrf -mno-mfcrf -mpopcntb -mno-popcntb -mfprnd -mno-fprnd @gol
-mnew-mnemonics -mold-mnemonics @gol
-mfull-toc -mminimal-toc -mno-fp-in-toc -mno-sum-in-toc @gol
-m64 -m32 -mxl-compat -mno-xl-compat -mpe @gol
*************** These @samp{-m} options are defined for
*** 10830,10835 ****
--- 10831,10842 ----
@itemx -mno-powerpc-gfxopt
@itemx -mpowerpc64
@itemx -mno-powerpc64
+ @itemx -mmfcrf
+ @itemx -mno-mfcrf
+ @itemx -mpopcntb
+ @itemx -mno-popcntb
+ @itemx -mfprnd
+ @itemx -mno-fprnd
@opindex mpower
@opindex mno-power
@opindex mpower2
*************** These @samp{-m} options are defined for
*** 10842,10853 ****
@opindex mno-powerpc-gfxopt
@opindex mpowerpc64
@opindex mno-powerpc64
GCC supports two related instruction set architectures for the
RS/6000 and PowerPC@. The @dfn{POWER} instruction set are those
instructions supported by the @samp{rios} chip set used in the original
RS/6000 systems and the @dfn{PowerPC} instruction set is the
! architecture of the Motorola MPC5xx, MPC6xx, MPC8xx microprocessors, and
! the IBM 4xx microprocessors.
Neither architecture is a subset of the other. However there is a
large common subset of instructions supported by both. An MQ
--- 10849,10866 ----
@opindex mno-powerpc-gfxopt
@opindex mpowerpc64
@opindex mno-powerpc64
+ @opindex mmfcrf
+ @opindex mno-mfcrf
+ @opindex mpopcntb
+ @opindex mno-popcntb
+ @opindex mfprnd
+ @opindex mno-fprnd
GCC supports two related instruction set architectures for the
RS/6000 and PowerPC@. The @dfn{POWER} instruction set are those
instructions supported by the @samp{rios} chip set used in the original
RS/6000 systems and the @dfn{PowerPC} instruction set is the
! architecture of the Freescale MPC5xx, MPC6xx, MPC8xx microprocessors, and
! the IBM 4xx, 6xx, and follow-on microprocessors.
Neither architecture is a subset of the other. However there is a
large common subset of instructions supported by both. An MQ
*************** General Purpose group, including floatin
*** 10875,10880 ****
--- 10888,10905 ----
use the optional PowerPC architecture instructions in the Graphics
group, including floating-point select.
+ The @option{-mmfcrf} option allows GCC to generate the move from
+ condition register field instruction implemented on the POWER4
+ processor and other processors that support the PowerPC V2.01
+ architecture.
+ The @option{-mpopcntb} option allows GCC to generate the popcount and
+ double precision FP reciprocal estimate instruction implemented on the
+ POWER5 processor and other processors that support the PowerPC V2.02
+ architecture.
+ The @option{-mfprnd} option allows GCC to generate the FP round to
+ integer instructions implemented on the POWER5+ processor and other
+ processors that support the PowerPC V2.03 architecture.
+
The @option{-mpowerpc64} option allows GCC to generate the additional
64-bit instructions that are found in the full PowerPC64 architecture
and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to
*************** Supported values for @var{cpu_type} are
*** 10913,10921 ****
@samp{601}, @samp{602}, @samp{603}, @samp{603e}, @samp{604},
@samp{604e}, @samp{620}, @samp{630}, @samp{740}, @samp{7400},
@samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
! @samp{860}, @samp{970}, @samp{8540}, @samp{common}, @samp{ec603e}, @samp{G3},
@samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3},
! @samp{power4}, @samp{power5}, @samp{powerpc}, @samp{powerpc64},
@samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}.
@option{-mcpu=common} selects a completely generic processor. Code
--- 10938,10947 ----
@samp{601}, @samp{602}, @samp{603}, @samp{603e}, @samp{604},
@samp{604e}, @samp{620}, @samp{630}, @samp{740}, @samp{7400},
@samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
! @samp{860}, @samp{970}, @samp{8540}, @samp{ec603e}, @samp{G3},
@samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3},
! @samp{power4}, @samp{power5}, @samp{power5+},
! @samp{common}, @samp{powerpc}, @samp{powerpc64},
@samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}.
@option{-mcpu=common} selects a completely generic processor. Code
*************** those options will run best on that proc
*** 10935,10953 ****
others.
The @option{-mcpu} options automatically enable or disable the
! following options: @option{-maltivec}, @option{-mhard-float},
! @option{-mmfcrf}, @option{-mmultiple}, @option{-mnew-mnemonics},
! @option{-mpower}, @option{-mpower2}, @option{-mpowerpc64},
! @option{-mpowerpc-gpopt}, @option{-mpowerpc-gfxopt},
! @option{-mstring}. The particular options set for any particular CPU
! will vary between compiler versions, depending on what setting seems
! to produce optimal code for that CPU; it doesn't necessarily reflect
! the actual hardware's capabilities. If you wish to set an individual
! option to a particular value, you may specify it after the
! @option{-mcpu} option, like @samp{-mcpu=970 -mno-altivec}.
On AIX, the @option{-maltivec} and @option{-mpowerpc64} options are
! not enabled or disabled by the @option{-mcpu} option at present, since
AIX does not have full support for these options. You may still
enable or disable them individually if you're sure it'll work in your
environment.
--- 10961,10980 ----
others.
The @option{-mcpu} options automatically enable or disable the
! following options: @option{-maltivec}, @option{-mfprnd},
! @option{-mhard-float}, @option{-mmfcrf}, @option{-mmultiple},
! @option{-mnew-mnemonics}, @option{-mpopcntb}, @option{-mpower},
! @option{-mpower2}, @option{-mpowerpc64}, @option{-mpowerpc-gpopt},
! @option{-mpowerpc-gfxopt}, @option{-mstring}. The particular options
! set for any particular CPU will vary between compiler versions,
! depending on what setting seems to produce optimal code for that CPU;
! it doesn't necessarily reflect the actual hardware's capabilities. If
! you wish to set an individual option to a particular value, you may
! specify it after the @option{-mcpu} option, like @samp{-mcpu=970
! -mno-altivec}.
On AIX, the @option{-maltivec} and @option{-mpowerpc64} options are
! not enabled or disabled by the @option{-mcpu} option at present because
AIX does not have full support for these options. You may still
enable or disable them individually if you're sure it'll work in your
environment.
Index: configure.ac
===================================================================
*** configure.ac (revision 106928)
--- configure.ac (working copy)
*************** foo: nop
*** 2763,2768 ****
--- 2763,2783 ----
[Define if your assembler supports popcntb field.])])
case $target in
+ *-*-aix*) conftest_s=' .machine "pwr5x"
+ .csect .text[[PR]]
+ frin 1,1';;
+ *) conftest_s=' .machine power5x
+ .text
+ frin 1,1';;
+ esac
+
+ gcc_GAS_CHECK_FEATURE([fp round support],
+ gcc_cv_as_powerpc_fprnd, [2,17,0],,
+ [$conftest_s],,
+ [AC_DEFINE(HAVE_AS_FPRND, 1,
+ [Define if your assembler supports fprnd.])])
+
+ case $target in
*-*-aix*) conftest_s=' .csect .text[[PR]]
LCF..0:
addis 11,30,_GLOBAL_OFFSET_TABLE_-LCF..0@ha';;
Index: config/rs6000/rs6000-c.c
===================================================================
*** config/rs6000/rs6000-c.c (revision 106928)
--- config/rs6000/rs6000-c.c (working copy)
*************** rs6000_cpu_cpp_builtins (cpp_reader *pfi
*** 94,101 ****
--- 94,111 ----
builtin_define ("_ARCH_PWR");
if (TARGET_POWERPC)
builtin_define ("_ARCH_PPC");
+ if (TARGET_PPC_GPOPT)
+ builtin_define ("_ARCH_PPCSQ");
+ if (TARGET_PPC_GFXOPT)
+ builtin_define ("_ARCH_PPCGR");
if (TARGET_POWERPC64)
builtin_define ("_ARCH_PPC64");
+ if (TARGET_MFCRF)
+ builtin_define ("_ARCH_PWR4");
+ if (TARGET_POPCNTB)
+ builtin_define ("_ARCH_PWR5");
+ if (TARGET_FPRND)
+ builtin_define ("_ARCH_PWR5X");
if (! TARGET_POWER && ! TARGET_POWER2 && ! TARGET_POWERPC)
builtin_define ("_ARCH_COM");
if (TARGET_ALTIVEC)
Index: config/rs6000/rs6000.opt
===================================================================
*** config/rs6000/rs6000.opt (revision 106928)
--- config/rs6000/rs6000.opt (working copy)
*************** Use PowerPC Graphics group optional inst
*** 54,64 ****
mmfcrf
Target Report Mask(MFCRF)
! Generate single field mfcr instruction
mpopcntb
Target Report Mask(POPCNTB)
! Use PowerPC/AS popcntb instruction
maltivec
Target Report Mask(ALTIVEC)
--- 54,68 ----
mmfcrf
Target Report Mask(MFCRF)
! Use PowerPC V2.01 single field mfcr instruction
mpopcntb
Target Report Mask(POPCNTB)
! Use PowerPC V2.02 popcntb instruction
!
! mfprnd
! Target Report Mask(FPRND)
! Use PowerPC V2.02 floating point rounding instructions
maltivec
Target Report Mask(ALTIVEC)
Index: config/rs6000/rs6000.c
===================================================================
*** config/rs6000/rs6000.c (revision 106928)
--- config/rs6000/rs6000.c (working copy)
*************** rs6000_override_options (const char *def
*** 1152,1157 ****
--- 1152,1160 ----
{"power5", PROCESSOR_POWER5,
POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
| MASK_MFCRF | MASK_POPCNTB},
+ {"power5+", PROCESSOR_POWER5,
+ POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
+ | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
{"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
{"powerpc64", PROCESSOR_POWERPC64,
POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
*************** rs6000_override_options (const char *def
*** 1177,1183 ****
POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
! | MASK_MFCRF)
};
rs6000_init_hard_regno_mode_ok ();
--- 1180,1186 ----
POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
! | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND)
};
rs6000_init_hard_regno_mode_ok ();
Index: config/rs6000/aix52.h
===================================================================
*** config/rs6000/aix52.h (revision 106928)
--- config/rs6000/aix52.h (working copy)
*************** do { \
*** 61,66 ****
--- 61,67 ----
%{mcpu=power3: -m620} \
%{mcpu=power4: -m620} \
%{mcpu=power5: -m620} \
+ %{mcpu=power5+: -m620} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rs64a: -mppc} \
%{mcpu=603: -m603} \
Index: config/rs6000/rs6000.h
===================================================================
*** config/rs6000/rs6000.h (revision 106928)
--- config/rs6000/rs6000.h (working copy)
***************
*** 72,77 ****
--- 72,78 ----
%{mcpu=power3: -mppc64} \
%{mcpu=power4: -mpower4} \
%{mcpu=power5: -mpower4} \
+ %{mcpu=power5+: -mpower4} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rios: -mpwr} \
%{mcpu=rios1: -mpwr} \
***************
*** 149,154 ****
--- 150,163 ----
#ifndef HAVE_AS_POPCNTB
#undef TARGET_POPCNTB
#define TARGET_POPCNTB 0
+ #endif
+
+ /* Define TARGET_FPRND if the target assembler does not support the
+ fp rounding instructions. */
+
+ #ifndef HAVE_AS_FPRND
+ #undef TARGET_FPRND
+ #define TARGET_FPRND 0
#endif
#ifndef TARGET_SECURE_PLT
Index: config/rs6000/rs6000.md
===================================================================
*** config/rs6000/rs6000.md (revision 106928)
--- config/rs6000/rs6000.md (working copy)
***************
*** 34,39 ****
--- 34,43 ----
(UNSPEC_MOVSI_GOT 8)
(UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
(UNSPEC_FCTIWZ 10)
+ (UNSPEC_FRIM 11)
+ (UNSPEC_FRIN 12)
+ (UNSPEC_FRIP 13)
+ (UNSPEC_FRIZ 14)
(UNSPEC_LD_MPIC 15) ; load_macho_picbase
(UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
(UNSPEC_TLSGD 17)
***************
*** 5315,5320 ****
--- 5319,5380 ----
UNSPEC_FCTIWZ))]
"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
"{fcirz|fctiwz} %0,%1"
+ [(set_attr "type" "fp")])
+
+ (define_insn "btruncdf2"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
+ "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "friz %0,%1"
+ [(set_attr "type" "fp")])
+
+ (define_insn "btruncsf2"
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
+ "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "frizs %0,%1"
+ [(set_attr "type" "fp")])
+
+ (define_insn "ceildf2"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
+ "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "frip %0,%1"
+ [(set_attr "type" "fp")])
+
+ (define_insn "ceilsf2"
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
+ "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "frips %0,%1"
+ [(set_attr "type" "fp")])
+
+ (define_insn "floordf2"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
+ "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "frim %0,%1"
+ [(set_attr "type" "fp")])
+
+ (define_insn "floorsf2"
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
+ "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "frims %0,%1"
+ [(set_attr "type" "fp")])
+
+ (define_insn "rounddf2"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
+ "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "frin %0,%1"
+ [(set_attr "type" "fp")])
+
+ (define_insn "roundsf2"
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
+ "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "frins %0,%1"
[(set_attr "type" "fp")])
; An UNSPEC is used so we don't have to support SImode in FP registers.