[PATCH, committed] PowerPC fixes

[David Edelsohn <dje at watson dot ibm dot com>]

	A recent patch adding get_attr_min_length changed the length of
unconditional jump instructions, which changed the bb-reorder heuristics
for PowerPC.  This patch restores the default value determined prior to
the change.

	Additionally, the Altivec patterns and builtins in GCC defined two
instructions that do not exist: vpkuhss and vpkuwss.  This patch removes
those references.

	Finally, this patch re-enables the plus_eqsi and neg_eq SCC
patterns that use the carry bit.

Bootstrapped and regression tested on powerpc-ibm-aix5.2.0.0.

David

	* config/rs6000/rs6000.c: Include params.h
	(optimization_options): Set max-grow-copy-bb-insns default to 16.
	(bdesc_2arg): Delete vpkuhss and vpkuwss.
	* config/rs6000/altivec.md (UNSPEC_VPKUHSS): Delete.
	(UNSPEC_VPKUWSS): Delete.
	(altivec_vpkuhss): Delete.
	(altivec_vpkuwss): Delete.
	* config/rs6000/rs6000.md (plus_eqsi): Remove optimize_size from
	final condition.
	(neg_eq0<mode>): Remove final condition.
	(neg_eq<mode>): Remove condition and split-condition.

Index: rs6000.c
===================================================================
*** rs6000.c	(revision 106478)
--- rs6000.c	(working copy)
***************
*** 54,59 ****
--- 54,60 ----
  #include "sched-int.h"
  #include "tree-gimple.h"
  #include "intl.h"
+ #include "params.h"
  #if TARGET_XCOFF
  #include "xcoffout.h"  /* get declarations of xcoff_*_section_name */
  #endif
*************** optimization_options (int level ATTRIBUT
*** 1573,1578 ****
--- 1574,1582 ----
      /* The Darwin libraries never set errno, so we might as well
         avoid calling them when that's the only reason we would.  */
      flag_errno_math = 0;
+ 
+   /* Double growth factor to counter reduced min jump length.  */
+   set_param_value ("max-grow-copy-bb-insns", 16);
  }
  
  /* Implement TARGET_HANDLE_OPTION.  */
*************** static struct builtin_description bdesc_
*** 5971,5979 ****
    { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
    { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
    { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
-   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
    { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
-   { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
    { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
    { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
    { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
--- 5975,5981 ----
Index: altivec.md
===================================================================
*** altivec.md	(revision 106478)
--- altivec.md	(working copy)
***************
*** 57,65 ****
     (UNSPEC_VPKUHUM       93)
     (UNSPEC_VPKUWUM       94)
     (UNSPEC_VPKPX         95)
-    (UNSPEC_VPKUHSS       96)
     (UNSPEC_VPKSHSS       97)
-    (UNSPEC_VPKUWSS       98)
     (UNSPEC_VPKSWSS       99)
     (UNSPEC_VPKUHUS      100)
     (UNSPEC_VPKSHUS      101)
--- 57,63 ----
***************
*** 1105,1120 ****
    "vpkpx %0,%1,%2"
    [(set_attr "type" "vecperm")])
  
- (define_insn "altivec_vpkuhss"
-   [(set (match_operand:V16QI 0 "register_operand" "=v")
-         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
-                        (match_operand:V8HI 2 "register_operand" "v")]
- 		      UNSPEC_VPKUHSS))
-    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
-   "TARGET_ALTIVEC"
-   "vpkuhss %0,%1,%2"
-   [(set_attr "type" "vecperm")])
- 
  (define_insn "altivec_vpkshss"
    [(set (match_operand:V16QI 0 "register_operand" "=v")
          (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
--- 1103,1108 ----
***************
*** 1123,1138 ****
     (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
    "TARGET_ALTIVEC"
    "vpkshss %0,%1,%2"
-   [(set_attr "type" "vecperm")])
- 
- (define_insn "altivec_vpkuwss"
-   [(set (match_operand:V8HI 0 "register_operand" "=v")
-         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
-                       (match_operand:V4SI 2 "register_operand" "v")]
- 		     UNSPEC_VPKUWSS))
-    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
-   "TARGET_ALTIVEC"
-   "vpkuwss %0,%1,%2"
    [(set_attr "type" "vecperm")])
  
  (define_insn "altivec_vpkswss"
--- 1111,1116 ----
Index: rs6000.md
===================================================================
*** rs6000.md	(revision 106478)
--- rs6000.md	(working copy)
***************
*** 11264,11270 ****
  	(plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
  			(match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
  		 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
!   "TARGET_32BIT && optimize_size"
    "@
     xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
     {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
--- 11264,11270 ----
  	(plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
  			(match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
  		 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
!   "TARGET_32BIT"
    "@
     xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
     {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
***************
*** 11364,11370 ****
    [(set (match_operand:P 0 "gpc_reg_operand" "=r")
  	(neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
  		     (const_int 0))))]
!   "optimize_size || TARGET_POWER"
    "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
    [(set_attr "type" "two")
     (set_attr "length" "8")])
--- 11364,11370 ----
    [(set (match_operand:P 0 "gpc_reg_operand" "=r")
  	(neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
  		     (const_int 0))))]
!   ""
    "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
    [(set_attr "type" "two")
     (set_attr "length" "8")])
***************
*** 11373,11381 ****
    [(set (match_operand:P 0 "gpc_reg_operand" "=r")
  	(neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
  		     (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
!   "optimize_size || TARGET_POWER"
    "#"
!   "optimize_size || TARGET_POWER"
    [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
    {
      if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
--- 11373,11381 ----
    [(set (match_operand:P 0 "gpc_reg_operand" "=r")
  	(neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
  		     (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
!   ""
    "#"
!   ""
    [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
    {
      if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)