picoChip port contribution

[Daniel Towner <daniel dot towner at picochip dot com>]

Hi all,

As discussed previously in the gcc mailing list, here is the picoChip 
port contribution. I will submit the relevent www updates in a separate 
patch sometime next week.

I have filed all the necessary paperwork with the FSF, and will act as 
the official maintainer for the port. I believe that I have fulfilled 
all the requirements for new port contibutions, but in the event that I 
have missed anything, I will try to fix it as soon as possible.

regards,

dan.

Index: gcc/config.gcc
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config.gcc,v
retrieving revision 1.566
diff -c -p -r1.566 config.gcc
*** gcc/config.gcc      28 Sep 2005 23:50:03 -0000      1.566
--- gcc/config.gcc      30 Sep 2005 15:56:12 -0000
*************** mips*-*-*)
*** 291,296 ****
--- 291,299 ----
       cpu_type=mips
       need_64bit_hwint=yes
       ;;
+ picochip-*-*)
+         cpu_type=picochip
+         ;;
 powerpc*-*-*)
       cpu_type=rs6000
       extra_headers="ppc-asm.h altivec.h spe.h"
*************** pdp11-*-bsd)
*** 1583,1588 ****
--- 1586,1594 ----
 pdp11-*-*)
       use_fixproto=yes
       ;;
+ picochip-*)
+         # Nothing special
+         ;;
 # port not yet contributed
 #powerpc-*-openbsd*)
 #     tmake_file="${tmake_file} rs6000/t-fprules "
Index: gcc/doc/contrib.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/contrib.texi,v
retrieving revision 1.67
diff -c -p -r1.67 contrib.texi
*** gcc/doc/contrib.texi        3 Aug 2005 16:35:26 -0000       1.67
--- gcc/doc/contrib.texi        30 Sep 2005 15:56:18 -0000
*************** Teemu Torma for thread safe exception ha
*** 888,893 ****
--- 888,896 ----
 Leonard Tower wrote parts of the parser, RTL generator, and RTL
 definitions, and of the VAX machine description.

+ @item
+ Daniel Towner contributed and maintains the picoChip port.
+
 @item
 Tom Tromey for internationalization support and for his many Java
 contributions and libgcj maintainership.
Index: gcc/doc/extend.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/extend.texi,v
retrieving revision 1.267
diff -c -p -r1.267 extend.texi
*** gcc/doc/extend.texi 22 Aug 2005 16:12:09 -0000      1.267
--- gcc/doc/extend.texi 30 Sep 2005 15:56:33 -0000
*************** instructions, but allow the compiler to
*** 5787,5792 ****
--- 5787,5793 ----
 * X86 Built-in Functions::
 * MIPS DSP Built-in Functions::
 * MIPS Paired-Single Support::
+ * picoChip Built-in Functions::
 * PowerPC AltiVec Built-in Functions::
 * SPARC VIS Built-in Functions::
 @end menu
*************** else
*** 7224,7229 ****
--- 7225,7266 ----
 @end smallexample
 @end table

+ @node picoChip Built-in Functions
+ @subsection picoChip Built-in Functions
+
+ GCC provides an interface to selected machine instructions from the
+ picoChip instruction set.
+
+ @table @code
+ @item int __builtin_sbc (int @var{value})
+ Sign bit count.  Return the number of consecutive bits in @var{value}
+ which have the same value as the sign-bit.  The result is the number of
+ leading sign bits minus one, giving the number of redundant sign bits in
+ @var{value}.
+
+ @item int __builtin_byteswap (int @var{value})
+ Byte swap.  Return the result of swapping the upper and lower bytes of
+ @var{value}.
+
+ @item int __builtin_brev (int @var{value})
+ Bit reversal.  Return the result of reversing the bits in
+ @var{value}.  Bit 15 is swapped with bit 0, bit 14 is swapped with bit 1,
+ and so on.
+
+ @item int __builtin_adds (int @var{x}, int @var{y})
+ Saturating addition.  Return the result of adding @var{x} and @var{y},
+ storing the value 32767 if the result overflows.
+
+ @item int __builtin_subs (int @var{x}, int @var{y})
+ Saturating subtraction.  Return the result of subtracting @var{y} from
+ @var{x}, storing the value -32768 if the the result overflows.
+
+ @item void __builtin_halt (void)
+ Halt.  The processor will stop execution.  This built-in is useful for
+ implementing assertions.
+
+ @end table
+
 @node PowerPC AltiVec Built-in Functions
 @subsection PowerPC AltiVec Built-in Functions

Index: gcc/doc/invoke.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/invoke.texi,v
retrieving revision 1.680
diff -c -p -r1.680 invoke.texi
*** gcc/doc/invoke.texi 30 Sep 2005 15:36:22 -0000      1.680
--- gcc/doc/invoke.texi 30 Sep 2005 15:56:50 -0000
*************** Objective-C and Objective-C++ Dialects}.
*** 624,629 ****
--- 624,633 ----
 -mbranch-expensive  -mbranch-cheap @gol
 -msplit  -mno-split  -munix-asm  -mdec-asm}

+ @emph{picoChip Options}
+ @gccoptlist{-mae=@var{ae_type} -mvliw-lookahead=@var{N}
+ -msymbol-as-address -mno-inefficient-warnings}
+
 @emph{PowerPC Options}
 See RS/6000 and PowerPC Options.

*************** platform.
*** 7086,7091 ****
--- 7090,7096 ----
 * MN10300 Options::
 * MS1 Options::
 * PDP-11 Options::
+ * picoChip Options::
 * PowerPC Options::
 * RS/6000 and PowerPC Options::
 * S/390 and zSeries Options::
*************** Use DEC assembler syntax.  This is the d
*** 10760,10765 ****
--- 10765,10818 ----
 PDP-11 target other than @samp{pdp11-*-bsd}.
 @end table

+ @node picoChip Options
+ @subsection picoChip Options
+ @cindex picoChip options
+
+ These @samp{-m} options are defined for picoChip implementations:
+
+ @table @gcctabopt
+
+ @item -mae=@var{ae_type}
+ @opindex mcpu
+ Set the instruction set, register set, and instruction scheduling
+ parameters for array element type @var{ae_type}.  Supported values
+ for @var{ae_type} are @samp{ANY}, @samp{MUL}, and @samp{MAC}.
+
+ @option{-mae=ANY} selects a completely generic AE type.  Code
+ generated with this option will run on any of the other AE types.  The
+ code will not be as efficient as it would be if compiled for a specific
+ AE type, and some types of operation (e.g., multiplication) will not
+ work properly on all types of AE.
+
+ @option{-mae=MUL} selects a MUL AE type.  This is the most useful AE type
+ for copiled code, and is the default.
+
+ @option{-mae=MAC} selects a DSP-style MAC AE.  Code compiled with this
+ option may suffer from poor performance of byte (char) manipulation,
+ since the DSP AE does not provide hardware support for byte load/stores.
+
+ @item -msymbol-as-address
+ Enable the compiler to directly use a symbol name as an address in a
+ load/store instruction, without first loading it into a
+ register.  Typically, the use of this option will generate larger
+ programs, which run faster than when the option isn't used.  However, the
+ results vary from program to program, so it is left as a user option,
+ rather than being permanently enabled.
+
+ @item -mno-inefficient-warnings
+ Disables warnings about the generation of inefficient code.  These
+ warnings can be generated, for example, when compiling code which
+ performs byte-level memory operations on the MAC AE type.  The MAC AE has
+ no hardware support for byte-level memory operations, so all byte
+ load/stores must be synthesised from word load/store operations.  This is
+ inefficient and a warning will be generated indicating to the programmer
+ that they should rewrite the code to avoid byte operations, or to target
+ an AE type which has the necessary hardware support.  This option enables
+ the warning to be turned off.
+
+ @end table
+
 @node PowerPC Options
 @subsection PowerPC Options
 @cindex PowerPC options
Index: gcc/doc/md.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/md.texi,v
retrieving revision 1.147
diff -c -p -r1.147 md.texi
*** gcc/doc/md.texi     30 Sep 2005 15:36:26 -0000      1.147
--- gcc/doc/md.texi     30 Sep 2005 15:56:58 -0000
*************** Constant that is one of -1, 4, -4, 7, 8,
*** 1777,1782 ****
--- 1777,1822 ----
 Floating point constant that is legal for store immediate
 @end table

+ @item picoChip family---@file{picochip.h}
+ @table @code
+ @item k
+ Stack register.
+
+ @item f
+ Pointer register.  A register which can be used to access memory without
+ supplying an offset.  Any other register can be used to access memory,
+ but will need a constant offset.  In the case of the offset being zero,
+ it is more efficient to use a pointer register, since this reduces code
+ size.
+
+ @item t
+ A twin register.  A register which may be paired with an adjacent
+ register to create a 32-bit register.
+
+ @item a
+ Any absolute memory address (e.g., symbolic constant, symbolic
+ constant + offset).
+
+ @item I
+ 4-bit signed integer.
+
+ @item J
+ 4-bit unsigned integer.
+
+ @item K
+ 8-bit signed integer.
+
+ @item M
+ Any constant whose absolute value is no greater than 4-bits.
+
+ @item N
+ 10-bit signed integer
+
+ @item O
+ 16-bit signed integer.
+
+ @end table
+
 @item PowerPC and IBM RS6000---@file{rs6000.h}
 @table @code
 @item b

--
============================================================================
Daniel Towner
picoChip Designs Ltd, Riverside Buildings, 108, Walcot Street, BATH, BA1 5BG
daniel.towner@picochip.com
+44 (0) 7786 702589

Attachment: picoGcc.tar.bz2
Description: application/bzip