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[PATCH, committed] PowerPC scheduling fixes
- From: David Edelsohn <dje at watson dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Fri, 23 Sep 2005 10:34:53 -0400
- Subject: [PATCH, committed] PowerPC scheduling fixes
While auditing the PowerPC scheduling information, both Pete and I
noticed some errors. I also took this opportunity to list the string and
load/store multiple instructions as a loads and stores that are cracked.
Bootstrapped and regression tested on powerpc-ibm-aix5.2.0.0
David
2005-09-23 David Edelsohn <edelsohn@gnu.org>
Pete Steinmetz <steinmtz@us.ibm.com>
* config/rs6000/rs6000.md (neg-minus-mult): Set type to dmul.
(rldic.): Set type to "compare".
(rldicr.): Same.
(movsf_hardfloat): Set type to mtjmpr for MTCTR/MTLR. Set type to
mfjmpr for MFCTR/MFLR.
(movdf_hardfloat64): Same.
(movdf_softfloat64): Same. Correct order of store and move types.
(movti_string): Set type to store_ux/load_ux.
(load_multiple): Set type to load_ux.
(store_multiple): Set type to store_ux.
(movmemsi): Set type to store_ux.
(output_cbranch direct_return): Set type to jmpreg.
(stmw): Set type to store_ux.
(lmw): Set type to load_ux.
* config/rs6000/40x.md (ppc403-store): Increase latency to 2.
* config/rs6000/440.md (ppc440-store): Increase latency to 6.
* config/rs6000/603.md (ppc603-store): Occupy LSU for 2 cycles.
* config/rs6000/6xx.md (ppc604-store): Increase latency to 3.
* config/rs6000/mpc.md (mpccore-store): Increase latency to 2.
* config/rs6000/rios1.md (rios1-store): Increase latency to 2.
(rios1-fpstore): Increase latency to 3.
* config/rs6000/rios2.md (rios2-store): Increase latency to 2.
* config/rs6000/rs64.md (rs64a-store): Increase latency to 2.
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.410
diff -c -p -r1.410 rs6000.md
*** rs6000.md 22 Sep 2005 15:03:27 -0000 1.410
--- rs6000.md 23 Sep 2005 14:24:20 -0000
***************
*** 4669,4675 ****
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
&& ! HONOR_SIGNED_ZEROS (SFmode)"
"{fnms|fnmsub} %0,%1,%2,%3"
! [(set_attr "type" "fp")])
(define_expand "sqrtsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
--- 4669,4675 ----
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
&& ! HONOR_SIGNED_ZEROS (SFmode)"
"{fnms|fnmsub} %0,%1,%2,%3"
! [(set_attr "type" "dmul")])
(define_expand "sqrtsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
***************
*** 6382,6388 ****
"@
rldic. %4,%1,%H2,%W3
#"
! [(set_attr "type" "delayed_compare")
(set_attr "length" "4,8")])
(define_split
--- 6382,6388 ----
"@
rldic. %4,%1,%H2,%W3
#"
! [(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_split
***************
*** 6416,6422 ****
"@
rldic. %0,%1,%H2,%W3
#"
! [(set_attr "type" "delayed_compare")
(set_attr "length" "4,8")])
(define_split
--- 6416,6422 ----
"@
rldic. %0,%1,%H2,%W3
#"
! [(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_split
***************
*** 6458,6464 ****
"@
rldicr. %4,%1,%H2,%S3
#"
! [(set_attr "type" "delayed_compare")
(set_attr "length" "4,8")])
(define_split
--- 6458,6464 ----
"@
rldicr. %4,%1,%H2,%S3
#"
! [(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_split
***************
*** 6492,6498 ****
"@
rldicr. %0,%1,%H2,%S3
#"
! [(set_attr "type" "delayed_compare")
(set_attr "length" "4,8")])
(define_split
--- 6492,6498 ----
"@
rldicr. %0,%1,%H2,%S3
#"
! [(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_split
***************
*** 6740,6746 ****
#
#
#"
! [(set_attr "type" "compare,delayed_compare,delayed_compare,compare,compare,delayed_compare,delayed_compare,compare,compare,compare,compare,compare")
(set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
(define_split
--- 6740,6746 ----
#
#
#"
! [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
(set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
(define_split
***************
*** 6791,6797 ****
#
#
#"
! [(set_attr "type" "compare,delayed_compare,delayed_compare,compare,compare,delayed_compare,delayed_compare,compare,compare,compare,compare,compare")
(set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
(define_split
--- 6791,6797 ----
#
#
#"
! [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
(set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
(define_split
***************
*** 7418,7424 ****
{cror 0,0,0|nop}
#
#"
! [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
(set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
(define_insn "*movsf_softfloat"
--- 7418,7424 ----
{cror 0,0,0|nop}
#
#"
! [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
(set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
(define_insn "*movsf_softfloat"
***************
*** 7440,7446 ****
#
#
{cror 0,0,0|nop}"
! [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
(set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
--- 7440,7446 ----
#
#
{cror 0,0,0|nop}"
! [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
(set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
***************
*** 7700,7706 ****
#
#
#"
! [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
(set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
(define_insn "*movdf_softfloat64"
--- 7700,7706 ----
#
#
#"
! [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
(set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
(define_insn "*movdf_softfloat64"
***************
*** 7719,7725 ****
#
#
{cror 0,0,0|nop}"
! [(set_attr "type" "load,store,*,*,*,*,*,*,*")
(set_attr "length" "4,4,4,4,4,8,12,16,4")])
(define_expand "movtf"
--- 7719,7725 ----
#
#
{cror 0,0,0|nop}"
! [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
(set_attr "length" "4,4,4,4,4,8,12,16,4")])
(define_expand "movtf"
***************
*** 8153,8159 ****
return \"#\";
}
}"
! [(set_attr "type" "store,store,*,load,load,*")])
(define_insn "*movti_ppc64"
[(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
--- 8153,8159 ----
return \"#\";
}
}"
! [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
(define_insn "*movti_ppc64"
[(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
***************
*** 8254,8260 ****
"TARGET_STRING && XVECLEN (operands[0], 0) == 8"
"*
{ return rs6000_output_load_multiple (operands); }"
! [(set_attr "type" "load")
(set_attr "length" "32")])
(define_insn "*ldmsi7"
--- 8254,8260 ----
"TARGET_STRING && XVECLEN (operands[0], 0) == 8"
"*
{ return rs6000_output_load_multiple (operands); }"
! [(set_attr "type" "load_ux")
(set_attr "length" "32")])
(define_insn "*ldmsi7"
***************
*** 8276,8282 ****
"TARGET_STRING && XVECLEN (operands[0], 0) == 7"
"*
{ return rs6000_output_load_multiple (operands); }"
! [(set_attr "type" "load")
(set_attr "length" "32")])
(define_insn "*ldmsi6"
--- 8276,8282 ----
"TARGET_STRING && XVECLEN (operands[0], 0) == 7"
"*
{ return rs6000_output_load_multiple (operands); }"
! [(set_attr "type" "load_ux")
(set_attr "length" "32")])
(define_insn "*ldmsi6"
***************
*** 8296,8302 ****
"TARGET_STRING && XVECLEN (operands[0], 0) == 6"
"*
{ return rs6000_output_load_multiple (operands); }"
! [(set_attr "type" "load")
(set_attr "length" "32")])
(define_insn "*ldmsi5"
--- 8296,8302 ----
"TARGET_STRING && XVECLEN (operands[0], 0) == 6"
"*
{ return rs6000_output_load_multiple (operands); }"
! [(set_attr "type" "load_ux")
(set_attr "length" "32")])
(define_insn "*ldmsi5"
***************
*** 8314,8320 ****
"TARGET_STRING && XVECLEN (operands[0], 0) == 5"
"*
{ return rs6000_output_load_multiple (operands); }"
! [(set_attr "type" "load")
(set_attr "length" "32")])
(define_insn "*ldmsi4"
--- 8314,8320 ----
"TARGET_STRING && XVECLEN (operands[0], 0) == 5"
"*
{ return rs6000_output_load_multiple (operands); }"
! [(set_attr "type" "load_ux")
(set_attr "length" "32")])
(define_insn "*ldmsi4"
***************
*** 8330,8336 ****
"TARGET_STRING && XVECLEN (operands[0], 0) == 4"
"*
{ return rs6000_output_load_multiple (operands); }"
! [(set_attr "type" "load")
(set_attr "length" "32")])
(define_insn "*ldmsi3"
--- 8330,8336 ----
"TARGET_STRING && XVECLEN (operands[0], 0) == 4"
"*
{ return rs6000_output_load_multiple (operands); }"
! [(set_attr "type" "load_ux")
(set_attr "length" "32")])
(define_insn "*ldmsi3"
***************
*** 8344,8350 ****
"TARGET_STRING && XVECLEN (operands[0], 0) == 3"
"*
{ return rs6000_output_load_multiple (operands); }"
! [(set_attr "type" "load")
(set_attr "length" "32")])
(define_expand "store_multiple"
--- 8344,8350 ----
"TARGET_STRING && XVECLEN (operands[0], 0) == 3"
"*
{ return rs6000_output_load_multiple (operands); }"
! [(set_attr "type" "load_ux")
(set_attr "length" "32")])
(define_expand "store_multiple"
***************
*** 8421,8427 ****
(match_operand:SI 10 "gpc_reg_operand" "r"))])]
"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
"{stsi|stswi} %2,%1,%O0"
! [(set_attr "type" "store")])
(define_insn "*stmsi7"
[(match_parallel 0 "store_multiple_operation"
--- 8421,8427 ----
(match_operand:SI 10 "gpc_reg_operand" "r"))])]
"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
"{stsi|stswi} %2,%1,%O0"
! [(set_attr "type" "store_ux")])
(define_insn "*stmsi7"
[(match_parallel 0 "store_multiple_operation"
***************
*** 8442,8448 ****
(match_operand:SI 9 "gpc_reg_operand" "r"))])]
"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
"{stsi|stswi} %2,%1,%O0"
! [(set_attr "type" "store")])
(define_insn "*stmsi6"
[(match_parallel 0 "store_multiple_operation"
--- 8442,8448 ----
(match_operand:SI 9 "gpc_reg_operand" "r"))])]
"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
"{stsi|stswi} %2,%1,%O0"
! [(set_attr "type" "store_ux")])
(define_insn "*stmsi6"
[(match_parallel 0 "store_multiple_operation"
***************
*** 8461,8467 ****
(match_operand:SI 8 "gpc_reg_operand" "r"))])]
"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
"{stsi|stswi} %2,%1,%O0"
! [(set_attr "type" "store")])
(define_insn "*stmsi5"
[(match_parallel 0 "store_multiple_operation"
--- 8461,8467 ----
(match_operand:SI 8 "gpc_reg_operand" "r"))])]
"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
"{stsi|stswi} %2,%1,%O0"
! [(set_attr "type" "store_ux")])
(define_insn "*stmsi5"
[(match_parallel 0 "store_multiple_operation"
***************
*** 8478,8484 ****
(match_operand:SI 7 "gpc_reg_operand" "r"))])]
"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
"{stsi|stswi} %2,%1,%O0"
! [(set_attr "type" "store")])
(define_insn "*stmsi4"
[(match_parallel 0 "store_multiple_operation"
--- 8478,8484 ----
(match_operand:SI 7 "gpc_reg_operand" "r"))])]
"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
"{stsi|stswi} %2,%1,%O0"
! [(set_attr "type" "store_ux")])
(define_insn "*stmsi4"
[(match_parallel 0 "store_multiple_operation"
***************
*** 8493,8499 ****
(match_operand:SI 6 "gpc_reg_operand" "r"))])]
"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
"{stsi|stswi} %2,%1,%O0"
! [(set_attr "type" "store")])
(define_insn "*stmsi3"
[(match_parallel 0 "store_multiple_operation"
--- 8493,8499 ----
(match_operand:SI 6 "gpc_reg_operand" "r"))])]
"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
"{stsi|stswi} %2,%1,%O0"
! [(set_attr "type" "store_ux")])
(define_insn "*stmsi3"
[(match_parallel 0 "store_multiple_operation"
***************
*** 8506,8512 ****
(match_operand:SI 5 "gpc_reg_operand" "r"))])]
"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
"{stsi|stswi} %2,%1,%O0"
! [(set_attr "type" "store")])
(define_expand "setmemsi"
[(parallel [(set (match_operand:BLK 0 "" "")
--- 8506,8512 ----
(match_operand:SI 5 "gpc_reg_operand" "r"))])]
"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
"{stsi|stswi} %2,%1,%O0"
! [(set_attr "type" "store_ux")])
(define_expand "setmemsi"
[(parallel [(set (match_operand:BLK 0 "" "")
***************
*** 8587,8593 ****
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
&& REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
! [(set_attr "type" "load")
(set_attr "length" "8")])
(define_insn ""
--- 8587,8593 ----
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
&& REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
! [(set_attr "type" "store_ux")
(set_attr "length" "8")])
(define_insn ""
***************
*** 8611,8617 ****
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
&& REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
! [(set_attr "type" "load")
(set_attr "length" "8")])
;; Move up to 24 bytes at a time. The fixed registers are needed because the
--- 8611,8617 ----
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
&& REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
! [(set_attr "type" "store_ux")
(set_attr "length" "8")])
;; Move up to 24 bytes at a time. The fixed registers are needed because the
***************
*** 8650,8656 ****
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
&& REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
! [(set_attr "type" "load")
(set_attr "length" "8")])
(define_insn ""
--- 8650,8656 ----
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
&& REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
! [(set_attr "type" "store_ux")
(set_attr "length" "8")])
(define_insn ""
***************
*** 8671,8677 ****
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
&& REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
! [(set_attr "type" "load")
(set_attr "length" "8")])
;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
--- 8671,8677 ----
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
&& REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
! [(set_attr "type" "store_ux")
(set_attr "length" "8")])
;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
***************
*** 8706,8712 ****
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
&& REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
! [(set_attr "type" "load")
(set_attr "length" "8")])
(define_insn ""
--- 8706,8712 ----
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
&& REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
! [(set_attr "type" "store_ux")
(set_attr "length" "8")])
(define_insn ""
***************
*** 8725,8731 ****
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
&& REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
! [(set_attr "type" "load")
(set_attr "length" "8")])
;; Move up to 8 bytes at a time.
--- 8725,8731 ----
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
&& REGNO (operands[4]) == 5"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
! [(set_attr "type" "store_ux")
(set_attr "length" "8")])
;; Move up to 8 bytes at a time.
***************
*** 8749,8755 ****
"TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
&& INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
! [(set_attr "type" "load")
(set_attr "length" "8")])
(define_insn ""
--- 8749,8755 ----
"TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
&& INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
! [(set_attr "type" "store_ux")
(set_attr "length" "8")])
(define_insn ""
***************
*** 8762,8768 ****
"TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
&& INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
! [(set_attr "type" "load")
(set_attr "length" "8")])
;; Move up to 4 bytes at a time.
--- 8762,8768 ----
"TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
&& INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
! [(set_attr "type" "store_ux")
(set_attr "length" "8")])
;; Move up to 4 bytes at a time.
***************
*** 8786,8792 ****
"TARGET_STRING && TARGET_POWER
&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
! [(set_attr "type" "load")
(set_attr "length" "8")])
(define_insn ""
--- 8786,8792 ----
"TARGET_STRING && TARGET_POWER
&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
! [(set_attr "type" "store_ux")
(set_attr "length" "8")])
(define_insn ""
***************
*** 8799,8805 ****
"TARGET_STRING && ! TARGET_POWER
&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
! [(set_attr "type" "load")
(set_attr "length" "8")])
;; Define insns that do load or store with update. Some of these we can
--- 8799,8805 ----
"TARGET_STRING && ! TARGET_POWER
&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
! [(set_attr "type" "store_ux")
(set_attr "length" "8")])
;; Define insns that do load or store with update. Some of these we can
***************
*** 12825,12831 ****
{
return output_cbranch (operands[0], NULL, 0, insn);
}"
! [(set_attr "type" "branch")
(set_attr "length" "4")])
(define_insn ""
--- 12825,12831 ----
{
return output_cbranch (operands[0], NULL, 0, insn);
}"
! [(set_attr "type" "jmpreg")
(set_attr "length" "4")])
(define_insn ""
***************
*** 12856,12862 ****
{
return output_cbranch (operands[0], NULL, 1, insn);
}"
! [(set_attr "type" "branch")
(set_attr "length" "4")])
;; Logic on condition register values.
--- 12856,12862 ----
{
return output_cbranch (operands[0], NULL, 1, insn);
}"
! [(set_attr "type" "jmpreg")
(set_attr "length" "4")])
;; Logic on condition register values.
***************
*** 13327,13333 ****
[(set (match_operand:SI 1 "memory_operand" "=m")
(match_operand:SI 2 "gpc_reg_operand" "r"))])]
"TARGET_MULTIPLE"
! "{stm|stmw} %2,%1")
(define_insn "*save_fpregs_<mode>"
[(match_parallel 0 "any_parallel_operand"
--- 13327,13334 ----
[(set (match_operand:SI 1 "memory_operand" "=m")
(match_operand:SI 2 "gpc_reg_operand" "r"))])]
"TARGET_MULTIPLE"
! "{stm|stmw} %2,%1"
! [(set_attr "type" "store_ux")])
(define_insn "*save_fpregs_<mode>"
[(match_parallel 0 "any_parallel_operand"
***************
*** 13402,13415 ****
; The load-multiple instructions have similar properties.
; Note that "load_multiple" is a name known to the machine-independent
! ; code that actually corresponds to the powerpc load-string.
(define_insn "*lmw"
[(match_parallel 0 "lmw_operation"
[(set (match_operand:SI 1 "gpc_reg_operand" "=r")
(match_operand:SI 2 "memory_operand" "m"))])]
"TARGET_MULTIPLE"
! "{lm|lmw} %1,%2")
(define_insn "*return_internal_<mode>"
[(return)
--- 13403,13417 ----
; The load-multiple instructions have similar properties.
; Note that "load_multiple" is a name known to the machine-independent
! ; code that actually corresponds to the PowerPC load-string.
(define_insn "*lmw"
[(match_parallel 0 "lmw_operation"
[(set (match_operand:SI 1 "gpc_reg_operand" "=r")
(match_operand:SI 2 "memory_operand" "m"))])]
"TARGET_MULTIPLE"
! "{lm|lmw} %1,%2"
! [(set_attr "type" "load_ux")])
(define_insn "*return_internal_<mode>"
[(return)
Index: 40x.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/40x.md,v
retrieving revision 1.13
diff -c -p -r1.13 40x.md
*** 40x.md 7 Jul 2005 14:30:13 -0000 1.13
--- 40x.md 23 Sep 2005 14:24:20 -0000
***************
*** 32,38 ****
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
! (define_insn_reservation "ppc403-store" 1
(and (eq_attr "type" "store,store_ux,store_u")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
--- 32,38 ----
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
! (define_insn_reservation "ppc403-store" 2
(and (eq_attr "type" "store,store_ux,store_u")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
Index: 440.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/440.md,v
retrieving revision 1.7
diff -c -p -r1.7 440.md
*** 440.md 7 Jul 2005 14:30:13 -0000 1.7
--- 440.md 23 Sep 2005 14:24:20 -0000
***************
*** 39,45 ****
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe")
! (define_insn_reservation "ppc440-store" 1
(and (eq_attr "type" "store,store_ux,store_u")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe")
--- 39,45 ----
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe")
! (define_insn_reservation "ppc440-store" 3
(and (eq_attr "type" "store,store_ux,store_u")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_l_pipe")
Index: 603.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/603.md,v
retrieving revision 1.14
diff -c -p -r1.14 603.md
*** 603.md 7 Jul 2005 14:30:13 -0000 1.14
--- 603.md 23 Sep 2005 14:24:20 -0000
***************
*** 46,52 ****
(define_insn_reservation "ppc603-store" 2
(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
(eq_attr "cpu" "ppc603"))
! "lsu_603")
(define_insn_reservation "ppc603-fpload" 2
(and (eq_attr "type" "fpload,fpload_ux,fpload_u")
--- 46,52 ----
(define_insn_reservation "ppc603-store" 2
(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
(eq_attr "cpu" "ppc603"))
! "lsu_603*2")
(define_insn_reservation "ppc603-fpload" 2
(and (eq_attr "type" "fpload,fpload_ux,fpload_u")
Index: 6xx.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/6xx.md,v
retrieving revision 1.13
diff -c -p -r1.13 6xx.md
*** 6xx.md 7 Jul 2005 14:30:13 -0000 1.13
--- 6xx.md 23 Sep 2005 14:24:20 -0000
***************
*** 58,64 ****
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"lsu_6xx")
! (define_insn_reservation "ppc604-store" 1
(and (eq_attr "type" "store,fpstore,store_ux,store_u,fpstore_ux,fpstore_u")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"lsu_6xx")
--- 58,64 ----
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"lsu_6xx")
! (define_insn_reservation "ppc604-store" 3
(and (eq_attr "type" "store,fpstore,store_ux,store_u,fpstore_ux,fpstore_u")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"lsu_6xx")
Index: mpc.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/mpc.md,v
retrieving revision 1.12
diff -c -p -r1.12 mpc.md
*** mpc.md 7 Jul 2005 14:30:13 -0000 1.12
--- mpc.md 23 Sep 2005 14:24:20 -0000
***************
*** 32,38 ****
(eq_attr "cpu" "mpccore"))
"lsu_mpc")
! (define_insn_reservation "mpccore-store" 1
(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
(eq_attr "cpu" "mpccore"))
"lsu_mpc")
--- 32,38 ----
(eq_attr "cpu" "mpccore"))
"lsu_mpc")
! (define_insn_reservation "mpccore-store" 2
(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
(eq_attr "cpu" "mpccore"))
"lsu_mpc")
Index: rios1.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rios1.md,v
retrieving revision 1.12
diff -c -p -r1.12 rios1.md
*** rios1.md 7 Jul 2005 14:30:13 -0000 1.12
--- rios1.md 23 Sep 2005 14:24:20 -0000
***************
*** 31,37 ****
(eq_attr "cpu" "rios1,ppc601"))
"iu_rios1")
! (define_insn_reservation "rios1-store" 1
(and (eq_attr "type" "store,store_ux,store_u")
(eq_attr "cpu" "rios1,ppc601"))
"iu_rios1")
--- 31,37 ----
(eq_attr "cpu" "rios1,ppc601"))
"iu_rios1")
! (define_insn_reservation "rios1-store" 2
(and (eq_attr "type" "store,store_ux,store_u")
(eq_attr "cpu" "rios1,ppc601"))
"iu_rios1")
***************
*** 46,52 ****
(eq_attr "cpu" "ppc601"))
"iu_rios1")
! (define_insn_reservation "rios1-fpstore" 1
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
(eq_attr "cpu" "rios1,ppc601"))
"iu_rios1+fpu_rios1")
--- 46,52 ----
(eq_attr "cpu" "ppc601"))
"iu_rios1")
! (define_insn_reservation "rios1-fpstore" 3
(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
(eq_attr "cpu" "rios1,ppc601"))
"iu_rios1+fpu_rios1")
Index: rios2.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rios2.md,v
retrieving revision 1.12
diff -c -p -r1.12 rios2.md
*** rios2.md 7 Jul 2005 14:30:13 -0000 1.12
--- rios2.md 23 Sep 2005 14:24:20 -0000
***************
*** 34,40 ****
(eq_attr "cpu" "rios2"))
"iu1_rios2|iu2_rios2")
! (define_insn_reservation "rios2-store" 1
(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
(eq_attr "cpu" "rios2"))
"iu1_rios2|iu2_rios2")
--- 34,40 ----
(eq_attr "cpu" "rios2"))
"iu1_rios2|iu2_rios2")
! (define_insn_reservation "rios2-store" 2
(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
(eq_attr "cpu" "rios2"))
"iu1_rios2|iu2_rios2")
Index: rs64.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs64.md,v
retrieving revision 1.13
diff -c -p -r1.13 rs64.md
*** rs64.md 7 Jul 2005 14:30:14 -0000 1.13
--- rs64.md 23 Sep 2005 14:24:20 -0000
***************
*** 31,37 ****
(eq_attr "cpu" "rs64a"))
"lsu_rs64")
! (define_insn_reservation "rs64a-store" 1
(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
(eq_attr "cpu" "rs64a"))
"lsu_rs64")
--- 31,37 ----
(eq_attr "cpu" "rs64a"))
"lsu_rs64")
! (define_insn_reservation "rs64a-store" 2
(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
(eq_attr "cpu" "rs64a"))
"lsu_rs64")