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[PATCH] Fix gen_rtx_MEM on ARM
- From: Richard Earnshaw <Richard dot Earnshaw at buzzard dot freeserve dot co dot uk>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Richard dot Earnshaw at buzzard dot freeserve dot co dot uk
- Date: Sat, 10 Sep 2005 09:30:52 +0100
- Subject: [PATCH] Fix gen_rtx_MEM on ARM
This patch fixes most of the places where we use gen_rtx_MEM in ARM/Thumb
code. There are a small number of places where I've left the old use, but
in those cases we are just trying to generate a temporary to assist with
emitting assembler code - the resulting RTL is never emitted into the insn
chain.
Tested on arm-elf and bootstrapped/tested on arm-netbsdelf2
R.
2005-09-10 Richard Earnshaw <richard.earnshaw@arm.com>
* arm.c (arm_gen_rotated_half_load): Delete.
(vfp_emit_fstmx, arm_set_return_address): Use gen_frame_mem.
(emit_multi_reg_push, emit_sfm, arm_expand_prologue)
(thumb_set_return_address): Likewise.
(thumb_load_double_from_address): Use adjust_address.
* arm.md (splits calling arm_gen_rotated_half_load): Delete.
(extendhsisi2_mem, movhi_bytes): Use change_address.
(movhi): Use widen_memory_access.
(reload_out_df): Use replace_equiv_address.
* arm-protos.h (arm_gen_rotated_half_load): Delete prototype.
Index: arm-protos.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm-protos.h,v
retrieving revision 1.91
diff -p -p -r1.91 arm-protos.h
*** arm-protos.h 19 Aug 2005 13:17:04 -0000 1.91
--- arm-protos.h 10 Sep 2005 08:13:58 -0000
*************** extern rtx arm_gen_load_multiple (int, i
*** 87,93 ****
extern rtx arm_gen_store_multiple (int, int, rtx, int, int,
rtx, HOST_WIDE_INT *);
extern int arm_gen_movmemqi (rtx *);
- extern rtx arm_gen_rotated_half_load (rtx);
extern enum machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx);
extern enum machine_mode arm_select_dominance_cc_mode (rtx, rtx,
HOST_WIDE_INT);
--- 87,92 ----
Index: arm.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.c,v
retrieving revision 1.478
diff -p -p -r1.478 arm.c
*** arm.c 2 Sep 2005 19:09:33 -0000 1.478
--- arm.c 10 Sep 2005 08:14:01 -0000
*************** arm_gen_movmemqi (rtx *operands)
*** 6117,6146 ****
into the top 16 bits of the word. We can assume that the address is
known to be alignable and of the form reg, or plus (reg, const). */
- rtx
- arm_gen_rotated_half_load (rtx memref)
- {
- HOST_WIDE_INT offset = 0;
- rtx base = XEXP (memref, 0);
-
- if (GET_CODE (base) == PLUS)
- {
- offset = INTVAL (XEXP (base, 1));
- base = XEXP (base, 0);
- }
-
- /* If we aren't allowed to generate unaligned addresses, then fail. */
- if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0))
- return NULL;
-
- base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
-
- if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
- return base;
-
- return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
- }
-
/* Select a dominance comparison mode if possible for a test of the general
form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
COND_OR == DOM_CC_X_AND_Y => (X && Y)
--- 6117,6122 ----
*************** vfp_emit_fstmx (int base_reg, int count)
*** 8128,8135 ****
XVECEXP (par, 0, 0)
= gen_rtx_SET (VOIDmode,
! gen_rtx_MEM (BLKmode,
! gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
gen_rtx_UNSPEC (BLKmode,
gen_rtvec (1, reg),
UNSPEC_PUSH_MULT));
--- 8104,8112 ----
XVECEXP (par, 0, 0)
= gen_rtx_SET (VOIDmode,
! gen_frame_mem (BLKmode,
! gen_rtx_PRE_DEC (BLKmode,
! stack_pointer_rtx)),
gen_rtx_UNSPEC (BLKmode,
gen_rtvec (1, reg),
UNSPEC_PUSH_MULT));
*************** vfp_emit_fstmx (int base_reg, int count)
*** 8141,8147 ****
XVECEXP (dwarf, 0, 0) = tmp;
tmp = gen_rtx_SET (VOIDmode,
! gen_rtx_MEM (DFmode, stack_pointer_rtx),
reg);
RTX_FRAME_RELATED_P (tmp) = 1;
XVECEXP (dwarf, 0, 1) = tmp;
--- 8118,8124 ----
XVECEXP (dwarf, 0, 0) = tmp;
tmp = gen_rtx_SET (VOIDmode,
! gen_frame_mem (DFmode, stack_pointer_rtx),
reg);
RTX_FRAME_RELATED_P (tmp) = 1;
XVECEXP (dwarf, 0, 1) = tmp;
*************** vfp_emit_fstmx (int base_reg, int count)
*** 8153,8162 ****
XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
tmp = gen_rtx_SET (VOIDmode,
! gen_rtx_MEM (DFmode,
! gen_rtx_PLUS (SImode,
! stack_pointer_rtx,
! GEN_INT (i * 8))),
reg);
RTX_FRAME_RELATED_P (tmp) = 1;
XVECEXP (dwarf, 0, i + 1) = tmp;
--- 8130,8139 ----
XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
tmp = gen_rtx_SET (VOIDmode,
! gen_frame_mem (DFmode,
! gen_rtx_PLUS (SImode,
! stack_pointer_rtx,
! GEN_INT (i * 8))),
reg);
RTX_FRAME_RELATED_P (tmp) = 1;
XVECEXP (dwarf, 0, i + 1) = tmp;
*************** emit_multi_reg_push (unsigned long mask)
*** 9851,9859 ****
XVECEXP (par, 0, 0)
= gen_rtx_SET (VOIDmode,
! gen_rtx_MEM (BLKmode,
! gen_rtx_PRE_DEC (BLKmode,
! stack_pointer_rtx)),
gen_rtx_UNSPEC (BLKmode,
gen_rtvec (1, reg),
UNSPEC_PUSH_MULT));
--- 9828,9836 ----
XVECEXP (par, 0, 0)
= gen_rtx_SET (VOIDmode,
! gen_frame_mem (BLKmode,
! gen_rtx_PRE_DEC (BLKmode,
! stack_pointer_rtx)),
gen_rtx_UNSPEC (BLKmode,
gen_rtvec (1, reg),
UNSPEC_PUSH_MULT));
*************** emit_multi_reg_push (unsigned long mask)
*** 9861,9867 ****
if (i != PC_REGNUM)
{
tmp = gen_rtx_SET (VOIDmode,
! gen_rtx_MEM (SImode, stack_pointer_rtx),
reg);
RTX_FRAME_RELATED_P (tmp) = 1;
XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
--- 9838,9844 ----
if (i != PC_REGNUM)
{
tmp = gen_rtx_SET (VOIDmode,
! gen_frame_mem (SImode, stack_pointer_rtx),
reg);
RTX_FRAME_RELATED_P (tmp) = 1;
XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
*************** emit_multi_reg_push (unsigned long mask)
*** 9882,9892 ****
if (i != PC_REGNUM)
{
! tmp = gen_rtx_SET (VOIDmode,
! gen_rtx_MEM (SImode,
plus_constant (stack_pointer_rtx,
4 * j)),
! reg);
RTX_FRAME_RELATED_P (tmp) = 1;
XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
}
--- 9859,9870 ----
if (i != PC_REGNUM)
{
! tmp
! = gen_rtx_SET (VOIDmode,
! gen_frame_mem (SImode,
plus_constant (stack_pointer_rtx,
4 * j)),
! reg);
RTX_FRAME_RELATED_P (tmp) = 1;
XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
}
*************** emit_sfm (int base_reg, int count)
*** 9939,9951 ****
XVECEXP (par, 0, 0)
= gen_rtx_SET (VOIDmode,
! gen_rtx_MEM (BLKmode,
! gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
gen_rtx_UNSPEC (BLKmode,
gen_rtvec (1, reg),
UNSPEC_PUSH_MULT));
tmp = gen_rtx_SET (VOIDmode,
! gen_rtx_MEM (XFmode, stack_pointer_rtx), reg);
RTX_FRAME_RELATED_P (tmp) = 1;
XVECEXP (dwarf, 0, 1) = tmp;
--- 9917,9930 ----
XVECEXP (par, 0, 0)
= gen_rtx_SET (VOIDmode,
! gen_frame_mem (BLKmode,
! gen_rtx_PRE_DEC (BLKmode,
! stack_pointer_rtx)),
gen_rtx_UNSPEC (BLKmode,
gen_rtvec (1, reg),
UNSPEC_PUSH_MULT));
tmp = gen_rtx_SET (VOIDmode,
! gen_frame_mem (XFmode, stack_pointer_rtx), reg);
RTX_FRAME_RELATED_P (tmp) = 1;
XVECEXP (dwarf, 0, 1) = tmp;
*************** emit_sfm (int base_reg, int count)
*** 9955,9963 ****
XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
tmp = gen_rtx_SET (VOIDmode,
! gen_rtx_MEM (XFmode,
! plus_constant (stack_pointer_rtx,
! i * 12)),
reg);
RTX_FRAME_RELATED_P (tmp) = 1;
XVECEXP (dwarf, 0, i + 1) = tmp;
--- 9934,9942 ----
XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
tmp = gen_rtx_SET (VOIDmode,
! gen_frame_mem (XFmode,
! plus_constant (stack_pointer_rtx,
! i * 12)),
reg);
RTX_FRAME_RELATED_P (tmp) = 1;
XVECEXP (dwarf, 0, i + 1) = tmp;
*************** arm_expand_prologue (void)
*** 10309,10315 ****
{
rtx dwarf;
insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
! insn = gen_rtx_MEM (SImode, insn);
insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
insn = emit_insn (insn);
--- 10288,10294 ----
{
rtx dwarf;
insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
! insn = gen_frame_mem (SImode, insn);
insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
insn = emit_insn (insn);
*************** arm_expand_prologue (void)
*** 10398,10404 ****
if (regs_ever_live[reg] && ! call_used_regs [reg])
{
insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
! insn = gen_rtx_MEM (V2SImode, insn);
insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
gen_rtx_REG (V2SImode, reg)));
RTX_FRAME_RELATED_P (insn) = 1;
--- 10377,10383 ----
if (regs_ever_live[reg] && ! call_used_regs [reg])
{
insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
! insn = gen_frame_mem (V2SImode, insn);
insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
gen_rtx_REG (V2SImode, reg)));
RTX_FRAME_RELATED_P (insn) = 1;
*************** arm_expand_prologue (void)
*** 10417,10423 ****
if (regs_ever_live[reg] && !call_used_regs[reg])
{
insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
! insn = gen_rtx_MEM (XFmode, insn);
insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
gen_rtx_REG (XFmode, reg)));
RTX_FRAME_RELATED_P (insn) = 1;
--- 10396,10402 ----
if (regs_ever_live[reg] && !call_used_regs[reg])
{
insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
! insn = gen_frame_mem (XFmode, insn);
insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
gen_rtx_REG (XFmode, reg)));
RTX_FRAME_RELATED_P (insn) = 1;
*************** arm_expand_prologue (void)
*** 10497,10503 ****
{
insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
GEN_INT (4));
! insn = gen_rtx_MEM (SImode, insn);
}
emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
--- 10476,10482 ----
{
insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
GEN_INT (4));
! insn = gen_frame_mem (SImode, insn);
}
emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
*************** thumb_load_double_from_address (rtx *ope
*** 13716,13724 ****
switch (GET_CODE (addr))
{
case REG:
! operands[2] = gen_rtx_MEM (SImode,
! plus_constant (XEXP (operands[1], 0), 4));
!
if (REGNO (operands[0]) == REGNO (addr))
{
output_asm_insn ("ldr\t%H0, %2", operands);
--- 13695,13702 ----
switch (GET_CODE (addr))
{
case REG:
! operands[2] = adjust_address (operands[1], SImode, 4);
!
if (REGNO (operands[0]) == REGNO (addr))
{
output_asm_insn ("ldr\t%H0, %2", operands);
*************** thumb_load_double_from_address (rtx *ope
*** 13733,13741 ****
case CONST:
/* Compute <address> + 4 for the high order load. */
! operands[2] = gen_rtx_MEM (SImode,
! plus_constant (XEXP (operands[1], 0), 4));
!
output_asm_insn ("ldr\t%0, %1", operands);
output_asm_insn ("ldr\t%H0, %2", operands);
break;
--- 13711,13718 ----
case CONST:
/* Compute <address> + 4 for the high order load. */
! operands[2] = adjust_address (operands[1], SImode, 4);
!
output_asm_insn ("ldr\t%0, %1", operands);
output_asm_insn ("ldr\t%H0, %2", operands);
break;
*************** thumb_load_double_from_address (rtx *ope
*** 13776,13783 ****
else
{
/* Compute <address> + 4 for the high order load. */
! operands[2] = gen_rtx_MEM (SImode,
! plus_constant (XEXP (operands[1], 0), 4));
/* If the computed address is held in the low order register
then load the high order register first, otherwise always
--- 13753,13760 ----
else
{
/* Compute <address> + 4 for the high order load. */
! operands[2] = adjust_address (operands[1], SImode, 4);
!
/* If the computed address is held in the low order register
then load the high order register first, otherwise always
*************** thumb_load_double_from_address (rtx *ope
*** 13798,13805 ****
case LABEL_REF:
/* With no registers to worry about we can just load the value
directly. */
! operands[2] = gen_rtx_MEM (SImode,
! plus_constant (XEXP (operands[1], 0), 4));
output_asm_insn ("ldr\t%H0, %2", operands);
output_asm_insn ("ldr\t%0, %1", operands);
--- 13775,13781 ----
case LABEL_REF:
/* With no registers to worry about we can just load the value
directly. */
! operands[2] = adjust_address (operands[1], SImode, 4);
output_asm_insn ("ldr\t%H0, %2", operands);
output_asm_insn ("ldr\t%0, %1", operands);
*************** arm_set_return_address (rtx source, rtx
*** 14694,14700 ****
addr = plus_constant (addr, delta);
}
! emit_move_insn (gen_rtx_MEM (Pmode, addr), source);
}
}
--- 14670,14676 ----
addr = plus_constant (addr, delta);
}
! emit_move_insn (gen_frame_mem (Pmode, addr), source);
}
}
*************** thumb_set_return_address (rtx source, rt
*** 14744,14750 ****
else
addr = plus_constant (addr, delta);
! emit_move_insn (gen_rtx_MEM (Pmode, addr), source);
}
else
emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
--- 14720,14726 ----
else
addr = plus_constant (addr, delta);
! emit_move_insn (gen_frame_mem (Pmode, addr), source);
}
else
emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
Index: arm.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.md,v
retrieving revision 1.205
diff -p -p -r1.205 arm.md
*** arm.md 20 Aug 2005 10:31:42 -0000 1.205
--- arm.md 10 Sep 2005 08:14:03 -0000
***************
*** 3390,3425 ****
(set_attr "predicable" "yes")]
)
- (define_split
- [(set (match_operand:SI 0 "s_register_operand" "")
- (zero_extend:SI (match_operand:HI 1 "alignable_memory_operand" "")))
- (clobber (match_operand:SI 2 "s_register_operand" ""))]
- "TARGET_ARM && (!arm_arch4)"
- [(set (match_dup 2) (match_dup 1))
- (set (match_dup 0) (lshiftrt:SI (match_dup 2) (const_int 16)))]
- "
- if ((operands[1] = arm_gen_rotated_half_load (operands[1])) == NULL)
- FAIL;
- "
- )
-
- (define_split
- [(set (match_operand:SI 0 "s_register_operand" "")
- (match_operator:SI 3 "shiftable_operator"
- [(zero_extend:SI (match_operand:HI 1 "alignable_memory_operand" ""))
- (match_operand:SI 4 "s_register_operand" "")]))
- (clobber (match_operand:SI 2 "s_register_operand" ""))]
- "TARGET_ARM && (!arm_arch4)"
- [(set (match_dup 2) (match_dup 1))
- (set (match_dup 0)
- (match_op_dup 3
- [(lshiftrt:SI (match_dup 2) (const_int 16)) (match_dup 4)]))]
- "
- if ((operands[1] = arm_gen_rotated_half_load (operands[1])) == NULL)
- FAIL;
- "
- )
-
(define_expand "zero_extendqisi2"
[(set (match_operand:SI 0 "s_register_operand" "")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
--- 3390,3395 ----
***************
*** 3721,3730 ****
rtx mem1, mem2;
rtx addr = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
! mem1 = gen_rtx_MEM (QImode, addr);
! MEM_COPY_ATTRIBUTES (mem1, operands[1]);
! mem2 = gen_rtx_MEM (QImode, plus_constant (addr, 1));
! MEM_COPY_ATTRIBUTES (mem2, operands[1]);
operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = mem1;
operands[2] = gen_reg_rtx (SImode);
--- 3691,3698 ----
rtx mem1, mem2;
rtx addr = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
! mem1 = change_address (operands[1], QImode, addr);
! mem2 = change_address (operands[1], QImode, plus_constant (addr, 1));
operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = mem1;
operands[2] = gen_reg_rtx (SImode);
***************
*** 3777,3811 ****
"sxtah%?\\t%0, %2, %1"
)
- (define_split
- [(set (match_operand:SI 0 "s_register_operand" "")
- (sign_extend:SI (match_operand:HI 1 "alignable_memory_operand" "")))
- (clobber (match_operand:SI 2 "s_register_operand" ""))]
- "TARGET_ARM && (!arm_arch4)"
- [(set (match_dup 2) (match_dup 1))
- (set (match_dup 0) (ashiftrt:SI (match_dup 2) (const_int 16)))]
- "
- if ((operands[1] = arm_gen_rotated_half_load (operands[1])) == NULL)
- FAIL;
- "
- )
-
- (define_split
- [(set (match_operand:SI 0 "s_register_operand" "")
- (match_operator:SI 3 "shiftable_operator"
- [(sign_extend:SI (match_operand:HI 1 "alignable_memory_operand" ""))
- (match_operand:SI 4 "s_register_operand" "")]))
- (clobber (match_operand:SI 2 "s_register_operand" ""))]
- "TARGET_ARM && (!arm_arch4)"
- [(set (match_dup 2) (match_dup 1))
- (set (match_dup 0)
- (match_op_dup 3
- [(ashiftrt:SI (match_dup 2) (const_int 16)) (match_dup 4)]))]
- "if ((operands[1] = arm_gen_rotated_half_load (operands[1])) == NULL)
- FAIL;
- "
- )
-
(define_expand "extendqihi2"
[(set (match_dup 2)
(ashift:SI (match_operand:QI 1 "general_operand" "")
--- 3745,3750 ----
***************
*** 4750,4761 ****
&& GET_CODE (base = XEXP (base, 0)) == REG))
&& REGNO_POINTER_ALIGN (REGNO (base)) >= 32)
{
- HOST_WIDE_INT new_offset = INTVAL (offset) & ~3;
rtx new;
! new = gen_rtx_MEM (SImode,
! plus_constant (base, new_offset));
! MEM_COPY_ATTRIBUTES (new, operands[1]);
emit_insn (gen_movsi (reg, new));
if (((INTVAL (offset) & 2) != 0)
^ (BYTES_BIG_ENDIAN ? 1 : 0))
--- 4689,4699 ----
&& GET_CODE (base = XEXP (base, 0)) == REG))
&& REGNO_POINTER_ALIGN (REGNO (base)) >= 32)
{
rtx new;
! new = widen_memory_access (operands[1], SImode,
! ((INTVAL (offset) & ~3)
! - INTVAL (offset)));
emit_insn (gen_movsi (reg, new));
if (((INTVAL (offset) & 2) != 0)
^ (BYTES_BIG_ENDIAN ? 1 : 0))
***************
*** 4882,4891 ****
rtx mem1, mem2;
rtx addr = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
! mem1 = gen_rtx_MEM (QImode, addr);
! MEM_COPY_ATTRIBUTES (mem1, operands[1]);
! mem2 = gen_rtx_MEM (QImode, plus_constant (addr, 1));
! MEM_COPY_ATTRIBUTES (mem2, operands[1]);
operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = mem1;
operands[2] = gen_reg_rtx (SImode);
--- 4820,4827 ----
rtx mem1, mem2;
rtx addr = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
! mem1 = change_address (operands[1], QImode, addr);
! mem2 = change_address (operands[1], QImode, plus_constant (addr, 1));
operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = mem1;
operands[2] = gen_reg_rtx (SImode);
***************
*** 5233,5239 ****
emit_insn (gen_addsi3 (operands[2], XEXP (XEXP (operands[0], 0), 0),
XEXP (XEXP (operands[0], 0), 1)));
! emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (DFmode, operands[2]),
operands[1]));
if (code == POST_DEC)
--- 5169,5176 ----
emit_insn (gen_addsi3 (operands[2], XEXP (XEXP (operands[0], 0), 0),
XEXP (XEXP (operands[0], 0), 1)));
! emit_insn (gen_rtx_SET (VOIDmode,
! replace_equiv_address (operands[0], operands[2]),
operands[1]));
if (code == POST_DEC)