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Re: unreviewed patch (ping N+1)
> Below is a patch, correcting/deleting the comments.
And here it is... :)
--- x/ms1.md 2005-08-22 11:30:05.000000000 -0400
+++ ms1.md 2005-08-22 11:15:14.000000000 -0400
@@ -18,54 +18,8 @@
;; along with GCC; see the file COPYING. If not, write to the Free
;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
;; 02110-1301, USA.
-
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-;; ::::::::::::::::::::
-;; ::
-;; :: UNSPEC_VOLATILE usage
-;; ::
-;; ::::::::::::::::::::
-;;
-;; 0 blockage
-;; 1 Enable interrupts
-;; 2 Disable interrupts
-;;
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: Attributes
-;; ::
-;; ::::::::::::::::::::
-
-;; The `define_attr' expression is used to define each attribute required by
-;; the target machine. It looks like:
-;;
-;; (define_attr NAME LIST-OF-VALUES DEFAULT)
-
-;; NAME is a string specifying the name of the attribute being defined.
-
-;; LIST-OF-VALUES is either a string that specifies a comma-separated list of
-;; values that can be assigned to the attribute, or a null string to indicate
-;; that the attribute takes numeric values.
-
-;; DEFAULT is an attribute expression that gives the value of this attribute
-;; for insns that match patterns whose definition does not include an explicit
-;; value for this attribute.
-
-;; For each defined attribute, a number of definitions are written to the
-;; `insn-attr.h' file. For cases where an explicit set of values is specified
-;; for an attribute, the following are defined:
-
-;; type:
-;; "branch" Changes the pc (and has a delay slot)
-;; "mem" Accesses memory space (and has a "delay" slot)
-;; "io" Accesses I/O space
-;; "arith" register and immediate operations
-;; "complex" multiple instructions
-;; "unknown" None of the above
-
+;; Attributes
(define_attr "type" "branch,mem,io,arith,complex,unknown"
(const_string "unknown") )
@@ -75,112 +29,7 @@
(define_attr "length" "" (const_int 4))
-/* This is description of pipeline hazards based on DFA. The
- following constructions can be used for this:
-
- o define_cpu_unit string [string]) describes a cpu functional unit
- (separated by comma).
-
- 1st operand: Names of cpu function units.
- 2nd operand: Name of automaton (see comments for
- DEFINE_AUTOMATON).
-
- All define_reservations and define_cpu_units should have unique
- names which can not be "nothing".
-
- o (exclusion_set string string) means that each CPU function unit
- in the first string can not be reserved simultaneously with each
- unit whose name is in the second string and vise versa. CPU
- units in the string are separated by commas. For example, it is
- useful for description CPU with fully pipelined floating point
- functional unit which can execute simultaneously only single
- floating point insns or only double floating point insns.
-
- o (presence_set string string) means that each CPU function unit in
- the first string can not be reserved unless at least one of units
- whose names are in the second string is reserved. This is an
- asymmetric relation. CPU units in the string are separated by
- commas. For example, it is useful for description that slot1 is
- reserved after slot0 reservation for a VLIW processor.
-
- o (absence_set string string) means that each CPU function unit in
- the first string can not be reserved only if each unit whose name
- is in the second string is not reserved. This is an asymmetric
- relation (actually exclusion set is analogous to this one but it
- is symmetric). CPU units in the string are separated by commas.
- For example, it is useful for description that slot0 can not be
- reserved after slot1 or slot2 reservation for a VLIW processor.
-
- o (define_bypass number out_insn_names in_insn_names) names bypass with
- given latency (the first number) from insns given by the first
- string (see define_insn_reservation) into insns given by the
- second string. Insn names in the strings are separated by
- commas.
-
- o (define_automaton string) describes names of an automaton
- generated and used for pipeline hazards recognition. The names
- are separated by comma. Actually it is possibly to generate the
- single automaton but unfortunately it can be very large. If we
- use more one automata, the summary size of the automata usually
- is less than the single one. The automaton name is used in
- define_cpu_unit. All automata should have unique names.
-
- o (define_reservation string string) names reservation (the first
- string) of cpu functional units (the 2nd string). Sometimes unit
- reservations for different insns contain common parts. In such
- case, you describe common part and use one its name (the 1st
- parameter) in regular expression in define_insn_reservation. All
- define_reservations, define results and define_cpu_units should
- have unique names which can not be "nothing".
-
- o (define_insn_reservation name default_latency condition regexpr)
- describes reservation of cpu functional units (the 3nd operand)
- for instruction which is selected by the condition (the 2nd
- parameter). The first parameter is used for output of debugging
- information. The reservations are described by a regular
- expression according the following syntax:
-
- regexp = regexp "," oneof
- | oneof
-
- oneof = oneof "|" allof
- | allof
-
- allof = allof "+" repeat
- | repeat
-
- repeat = element "*" number
- | element
-
- element = cpu_function_name
- | reservation_name
- | result_name
- | "nothing"
- | "(" regexp ")"
-
- 1. "," is used for describing start of the next cycle in
- reservation.
-
- 2. "|" is used for describing the reservation described by the
- first regular expression *or* the reservation described by
- the second regular expression *or* etc.
-
- 3. "+" is used for describing the reservation described by the
- first regular expression *and* the reservation described by
- the second regular expression *and* etc.
-
- 4. "*" is used for convinience and simply means sequence in
- which the regular expression are repeated NUMBER times with
- cycle advancing (see ",").
-
- 5. cpu function unit name which means reservation.
-
- 6. reservation name -- see define_reservation.
-
- 7. string "nothing" means no units reservation.
-
-*/
-
+;; DFA scheduler.
(define_automaton "other")
(define_cpu_unit "decode_unit" "other")
(define_cpu_unit "memory_unit" "other")
@@ -207,11 +56,7 @@
(define_bypass 3 "io_access" "branch_access")
-;; ::::::::::::::::::::
-;; ::
-;; :: Delay Slots
-;; ::
-;; ::::::::::::::::::::
+;; Delay Slots
;; The ms1 does not allow branches in the delay slot.
;; The ms1 does not allow back to back memory or io instruction.
@@ -223,41 +68,6 @@
[(eq_attr "type" "arith") (nil) (nil)])
-;; ::::::::::::::::::::
-;; ::
-;; :: Notes on Patterns
-;; ::
-;; ::::::::::::::::::::
-
-;; If you need to construct a sequence of assembler instructions in order
-;; to implement a pattern be sure to escape any backslashes and double quotes
-;; that you use, eg:
-;;
-;; (define_insn "an example"
-;; [(some rtl)]
-;; ""
-;; "*
-;; { static char buffer [100];
-;; sprintf (buffer, \"insn \\t %d\", REGNO (operands[1]));
-;; return buffer;
-;; }"
-;; )
-;;
-;; Also if there is more than one instruction, they can be seperated by \\;
-;; which is a space saving synonym for \\n\\t:
-;;
-;; (define_insn "another example"
-;; [(some rtl)]
-;; ""
-;; "*
-;; { static char buffer [100];
-;; sprintf (buffer, \"insn1 \\t %d\\;insn2 \\t %%1\",
-;; REGNO (operands[1]));
-;; return buffer;
-;; }"
-;; )
-;;
-
;; Issue 64382
;; This pattern implements the decrement and branch non-zero instruction
;; which can be used by gcc loop optimizer under certain conditions.
@@ -314,96 +124,7 @@
""
)
-;; ::::::::::::::::::::
-;; ::
-;; :: Moves
-;; ::
-;; ::::::::::::::::::::
-
-;; Wrap moves in define_expand to prevent memory->memory moves from being
-;; generated at the RTL level, which generates better code for most machines
-;; which can't do mem->mem moves.
-
-;; If operand 0 is a `subreg' with mode M of a register whose own mode is wider
-;; than M, the effect of this instruction is to store the specified value in
-;; the part of the register that corresponds to mode M. The effect on the rest
-;; of the register is undefined.
-
-;; This class of patterns is special in several ways. First of all, each of
-;; these names *must* be defined, because there is no other way to copy a datum
-;; from one place to another.
-
-;; Second, these patterns are not used solely in the RTL generation pass. Even
-;; the reload pass can generate move insns to copy values from stack slots into
-;; temporary registers. When it does so, one of the operands is a hard
-;; register and the other is an operand that can need to be reloaded into a
-;; register.
-
-;; Therefore, when given such a pair of operands, the pattern must
-;; generate RTL which needs no reloading and needs no temporary
-;; registers--no registers other than the operands. For example, if
-;; you support the pattern with a `define_expand', then in such a
-;; case the `define_expand' mustn't call `force_reg' or any other such
-;; function which might generate new pseudo registers.
-
-;; This requirement exists even for subword modes on a RISC machine
-;; where fetching those modes from memory normally requires several
-;; insns and some temporary registers. Look in `spur.md' to see how
-;; the requirement can be satisfied.
-
-;; During reload a memory reference with an invalid address may be passed as an
-;; operand. Such an address will be replaced with a valid address later in the
-;; reload pass. In this case, nothing may be done with the address except to
-;; use it as it stands. If it is copied, it will not be replaced with a valid
-;; address. No attempt should be made to make such an address into a valid
-;; address and no routine (such as `change_address') that will do so may be
-;; called. Note that `general_operand' will fail when applied to such an
-;; address.
-;;
-;; The global variable `reload_in_progress' (which must be explicitly declared
-;; if required) can be used to determine whether such special handling is
-;; required.
-;;
-;; The variety of operands that have reloads depends on the rest of
-;; the machine description, but typically on a RISC machine these can
-;; only be pseudo registers that did not get hard registers, while on
-;; other machines explicit memory references will get optional
-;; reloads.
-;;
-;; If a scratch register is required to move an object to or from memory, it
-;; can be allocated using `gen_reg_rtx' prior to reload. But this is
-;; impossible during and after reload. If there are cases needing scratch
-;; registers after reload, you must define `SECONDARY_INPUT_RELOAD_CLASS' and
-;; perhaps also `SECONDARY_OUTPUT_RELOAD_CLASS' to detect them, and provide
-;; patterns `reload_inM' or `reload_outM' to handle them.
-
-;; The constraints on a `moveM' must permit moving any hard register to any
-;; other hard register provided that `HARD_REGNO_MODE_OK' permits mode M in
-;; both registers and `REGISTER_MOVE_COST' applied to their classes returns a
-;; value of 2.
-
-;; It is obligatory to support floating point `moveM' instructions
-;; into and out of any registers that can hold fixed point values,
-;; because unions and structures (which have modes `SImode' or
-;; `DImode') can be in those registers and they may have floating
-;; point members.
-
-;; There may also be a need to support fixed point `moveM' instructions in and
-;; out of floating point registers. Unfortunately, I have forgotten why this
-;; was so, and I don't know whether it is still true. If `HARD_REGNO_MODE_OK'
-;; rejects fixed point values in floating point registers, then the constraints
-;; of the fixed point `moveM' instructions must be designed to avoid ever
-;; trying to reload into a floating point register.
-
-;; Some implementations of the MorphoRISC-I do not have byte loads and
-;; stores. These operations must be synthesized. Note that the
-;; code for the loadqi and storeqi assumes that
-;; the two least significant bits are ignored.
-
-;; loadqi
-;; operand 0 location of result
-;; operand 1 memory address
-;; operand 2 temp, shift count
+;; Moves
(define_expand "loadqi"
[
@@ -923,11 +644,7 @@
)
-;; ::::::::::::::::::::
-;; ::
-;; :: Reloads
-;; ::
-;; ::::::::::::::::::::
+;; Reloads
;; Like `movM', but used when a scratch register is required to move between
;; operand 0 and operand 1. Operand 2 describes the scratch register. See the
@@ -1067,26 +784,7 @@
}")
-;; ::::::::::::::::::::
-;; ::
-;; :: Conversions
-;; ::
-;; ::::::::::::::::::::
-
-;; Signed conversions from a smaller integer to a larger integer
-;;
-;; These operations are optional. If they are not
-;; present GCC will synthesise them for itself
-;;
-;; Morpho does not have any instructions to do type conversion
-;; so there are not any templates in this section.
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: 32 bit Integer arithmetic
-;; ::
-;; ::::::::::::::::::::
+;; 32 bit Integer arithmetic
;; Addition
(define_insn "addsi3"
@@ -1124,11 +822,7 @@
(set_attr "type" "arith,arith")])
-;; ::::::::::::::::::::
-;; ::
-;; :: 32 bit Integer Shifts and Rotates
-;; ::
-;; ::::::::::::::::::::
+;; 32 bit Integer Shifts and Rotates
;; Arithmetic Shift Left
(define_insn "ashlsi3"
@@ -1167,11 +861,7 @@
(set_attr "type" "arith,arith")])
-;; ::::::::::::::::::::
-;; ::
-;; :: 32 Bit Integer Logical operations
-;; ::
-;; ::::::::::::::::::::
+;; 32 Bit Integer Logical operations
;; Logical AND, 32 bit integers
(define_insn "andsi3"
@@ -1220,11 +910,7 @@
(set_attr "type" "arith")])
-;; ::::::::::::::::::::
-;; ::
-;; :: Multiply
-;; ::
-;; ::::::::::::::::::::
+;; Multiply
(define_insn "mulhisi3"
[(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -1238,11 +924,7 @@
(set_attr "type" "arith,arith")])
-;; ::::::::::::::::::::
-;; ::
-;; :: Comparisons
-;; ::
-;; ::::::::::::::::::::
+;; Comparisons
;; Note, we store the operands in the comparison insns, and use them later
;; when generating the branch or scc operation.
@@ -1261,34 +943,7 @@
}")
-;; ::::::::::::::::::::
-;; ::
-;; :: Branches
-;; ::
-;; ::::::::::::::::::::
-
-;; Define_expands called by the machine independent part of the compiler
-;; to allocate a new comparison register. Each of these named patterns
-;; must be present, and they cannot be amalgamated into one pattern.
-;;
-;; If a fixed condition code register is being used, (as opposed to, say,
-;; using cc0), then the expands should look like this:
-;;
-;; (define_expand "<name_of_test>"
-;; [(set (reg:CC <number_of_CC_register>)
-;; (compare:CC (match_dup 1)
-;; (match_dup 2)))
-;; (set (pc)
-;; (if_then_else (eq:CC (reg:CC <number_of_CC_register>)
-;; (const_int 0))
-;; (label_ref (match_operand 0 "" ""))
-;; (pc)))]
-;; ""
-;; "{
-;; operands[1] = ms1_compare_op0;
-;; operands[2] = ms1_compare_op1;
-;; }"
-;; )
+;; Branches
(define_expand "beq"
[(use (match_operand 0 "" ""))]
@@ -1419,31 +1074,6 @@
DONE;
}")
-;; Actual branches. We must allow for the (label_ref) and the (pc) to be
-;; swapped. If they are swapped, it reverses the sense of the branch.
-;;
-;; Note - unlike the define expands above, these patterns can be amalgamated
-;; into one pattern for branch-if-true and one for branch-if-false. This does
-;; require an operand operator to select the correct branch mnemonic.
-;;
-;; If a fixed condition code register is being used, (as opposed to, say,
-;; using cc0), then the expands could look like this:
-;;
-;; (define_insn "*branch_true"
-;; [(set (pc)
-;; (if_then_else (match_operator:CC 0 "comparison_operator"
-;; [(reg:CC <number_of_CC_register>)
-;; (const_int 0)])
-;; (label_ref (match_operand 1 "" ""))
-;; (pc)))]
-;; ""
-;; "b%B0 %1"
-;; [(set_attr "length" "4")]
-;; )
-;;
-;; In the above example the %B is a directive to ms1_print_operand()
-;; to decode and print the correct branch mnemonic.
-
(define_insn "*beq_true"
[(set (pc)
(if_then_else (eq (match_operand:SI 0 "reg_or_0_operand" "rJ")
@@ -1581,32 +1211,13 @@
;; converted to the signed operations above.
-;; ::::::::::::::::::::
-;; ::
-;; :: Set flag operations
-;; ::
-;; ::::::::::::::::::::
+;; Set flag operations
;; "seq", "sne", "slt", "sle", "sgt", "sge", "sltu", "sleu",
;; "sgtu", and "sgeu" don't exist as regular instruction on the
;; ms1, so these are not defined
-
-;; ::::::::::::::::::::
-;; ::
-;; :: Call and branch instructions
-;; ::
-;; ::::::::::::::::::::
-
-;; Subroutine call instruction returning no value. Operand 0 is the function
-;; to call; operand 1 is the number of bytes of arguments pushed (in mode
-;; `SImode', except it is normally a `const_int'); operand 2 is the number of
-;; registers used as operands.
-
-;; On most machines, operand 2 is not actually stored into the RTL pattern. It
-;; is supplied for the sake of some RISC machines which need to put this
-;; information into the assembler code; they can put it in the RTL instead of
-;; operand 1.
+;; Call and branch instructions
(define_expand "call"
[(parallel [(call (mem:SI (match_operand:SI 0 "register_operand" ""))
@@ -1628,13 +1239,6 @@
[(set_attr "length" "4")
(set_attr "type" "branch")])
-;; Subroutine call instruction returning a value. Operand 0 is the hard
-;; register in which the value is returned. There are three more operands, the
-;; same as the three operands of the `call' instruction (but with numbers
-;; increased by one).
-
-;; Subroutines that return `BLKmode' objects use the `call' insn.
-
(define_expand "call_value"
[(parallel [(set (match_operand 0 "register_operand" "")
(call (mem:SI (match_operand:SI 1 "register_operand" ""))
@@ -1707,22 +1311,6 @@
[(set_attr "length" "4")
(set_attr "type" "branch")])
-;; Instruction to jump to a variable address. This is a low-level capability
-;; which can be used to implement a dispatch table when there is no `casesi'
-;; pattern. Either the 'casesi' pattern or the 'tablejump' pattern, or both,
-;; MUST be present in this file.
-
-;; This pattern requires two operands: the address or offset, and a label which
-;; should immediately precede the jump table. If the macro
-;; `CASE_VECTOR_PC_RELATIVE' is defined then the first operand is an offset
-;; which counts from the address of the table; otherwise, it is an absolute
-;; address to jump to. In either case, the first operand has mode `Pmode'.
-
-;; The `tablejump' insn is always the last insn before the jump table it uses.
-;; Its assembler code normally has no need to use the second operand, but you
-;; should incorporate it in the RTL pattern so that the jump optimizer will not
-;; delete the table as unreachable code.
-
(define_insn "tablejump"
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
(use (label_ref (match_operand 1 "" "")))]
@@ -1732,18 +1320,6 @@
(set_attr "type" "branch")])
-;; ::::::::::::::::::::
-;; ::
-;; :: Prologue and Epilogue instructions
-;; ::
-;; ::::::::::::::::::::
-
-;; Called after register allocation to add any instructions needed for the
-;; prologue. Using a prologue insn is favored compared to putting all of the
-;; instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
-;; to intermix instructions with the saves of the caller saved registers. In
-;; some cases, it might be necessary to emit a barrier instruction as the last
-;; insn to prevent such scheduling.
(define_expand "prologue"
[(const_int 1)]
""
@@ -1753,12 +1329,6 @@
DONE;
}")
-;; Called after register allocation to add any instructions needed for the
-;; epilogue. Using a epilogue insn is favored compared to putting all of the
-;; instructions in the FUNCTION_EPILOGUE macro, since it allows the scheduler
-;; to intermix instructions with the restires of the caller saved registers.
-;; In some cases, it might be necessary to emit a barrier instruction as the
-;; first insn to prevent such scheduling.
(define_expand "epilogue"
[(const_int 2)]
""
@@ -1787,15 +1357,7 @@
[(const_int 1)]
"ms1_emit_eh_epilogue (operands); DONE;"
)
-
-
-;; ::::::::::::::::::::
-;; ::
-;; :: Miscellaneous instructions
-;; ::
-;; ::::::::::::::::::::
-
;; No operation, needed in case the user uses -g but not -O.
(define_insn "nop"
[(const_int 0)]
@@ -1804,6 +1366,17 @@
[(set_attr "length" "4")
(set_attr "type" "arith")])
+;; ::::::::::::::::::::
+;; ::
+;; :: UNSPEC_VOLATILE usage
+;; ::
+;; ::::::::::::::::::::
+;;
+;; 0 blockage
+;; 1 Enable interrupts
+;; 2 Disable interrupts
+;;
+
;; Pseudo instruction that prevents the scheduler from moving code above this
;; point.
(define_insn "blockage"