This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: [patch] Fix behavior of TER on unrolled loops
> Of course, also taking things to the extreme and wanting middle-end to know
> every single bit of architecture features is wrong. But knowing just enough
> so that it does not make changes that would make proper optimization in later,
> lower level optimizers impossible seems more correct to me.
The middle end knowing almost anything about the target architecture
besides very very simple things (Caches for example, which are
relatively "cross-architecture", and possibly a simple integer/fp
register count), means it's no longer a target independent middle end.
Also, how is TER, or anything in the middle end, supposed to be
accurately estimating register pressure when there are 20 optimization
passes that run after it?
If you make them all worry about what they are going to do with
registers by the time it gets to machine code, you'll get nowhere.