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[committed] S/390: Support for the new IBM System z9 109 mainframe
- From: Andreas Krebbel <krebbel1 at de dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Ulrich dot Weigand at de dot ibm dot com
- Date: Wed, 17 Aug 2005 13:13:51 +0200
- Subject: [committed] S/390: Support for the new IBM System z9 109 mainframe
Hello,
IBM recently presented a new mainframe following the z990:
http://www-03.ibm.com/servers/systems/systemz9/z9109/
>From a compiler point of view the most important cpu feature
is the extended immediate facility. This feature introduces
a bunch of instructions allowing for 32bit constants to be
used for a lot of operations.
The attached patch provides support of these instructions for
gcc. Code for the IBM System z9 109 can be compiled using the
-march=z9-109 switch.
I've comitted this patch to mainline gcc repository.
Ulrich reviewed and approved it offline.
Bye,
-Andreas-
2005-08-16 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
Andreas Krebbel <krebbel1@de.ibm.com>
* config.gcc: Added z9-109 switch.
* config/s390/2084.md ("x_int", "x_agen", "x_lr", "x_la", "x_larl",
"x_load", "x_store", "x_branch", "x_call", "x_mul_hi", "x_mul_sidi",
"x_div", "x_sem", "x_cs", "x_vs", "x_stm", "x_lm", "x_other",
"x_fsimpdf", "x_fsimpsf", "x_fdivdf", "x_fdivsf", "x_floaddf",
"x_floadsf", "x_fstore_df", "x_fstoresf", "x_ftoi", "x_itof"): Enable
for "z9_109" cpu attribute.
* config/s390/s390.c (z9_109_cost): New processor cost structure.
(CONST_OK_FOR_Os, CONST_OK_FOR_Op, CONST_OK_FOR_On): New macros.
(s390_handle_arch_option): Added z9-109 switch.
(override_options): Set respective cost function for z9-109.
(s390_const_ok_for_constraint_p): New constraints Os, Op, On.
(legitimate_reload_constant_p): Accept extended immediates.
(print_operand): Three new output modifiers added: k, m and o.
(s390_adjust_priority, s390_issue_rate): Handle Z9_109 like Z990.
(s390_output_mi_thunk): Use extended immediate when possible.
* config/s390/s390.h (processor_flags): Added PF_EXTIMM.
(TARGET_CPU_EXTIMM, TARGET_EXTIMM): New macros.
(CONSTRAINT_LEN): Added length of O constraint.
(CLZ_DEFINED_VALUE_AT_ZERO): Definition added.
* config/s390/s390.md ("cpu"): New value z9_109 added.
("*tstdi_extimm", "*tstdi_ccconly_extimm", "*tstsi_extimm",
"*tstsi_cconly_extimm", "*movdi_64extimm", "*extendhidi2_extimm",
"*extendqidi2_extimm", "*extendhisi2_extimm", "*extendqisi2_extimm",
"*zero_extend<mode>si2_extimm", "*anddi3_extimm", "*iordi3_extimm",
"*xordi3_extimm", "clzdi2", "clztidi2"): New patterns.
("*tstdi", "*tstsi", "*movdi_64", "*extendhisi2", "*extendqisi2",
"*zero_extend<mode>si2_64", "zero_extendqihi2", "*zero_extendqihi2_64",
"*anddi3", "*iordi3", "*xordi3"): Disable for TARGET_EXTIMM.
("*cmpdi_cct", "*cmpsi_cct", "*cmpdi_ccs", "*cmpsi_ccs", "*cmpdi_ccu",
"*cmpsi_ccu", "*movsi_zarch", "*adddi3_imm_cc", "*adddi3_carry1_cc",
"*adddi3_carry2_cc", "*adddi3_cc", "*adddi3_64", "*addsi3_imm_cc",
"*addsi3_carry1_cc", "*addsi3_carry2_cc", "*addsi3_cc", "addsi3",
"*andsi3_cc", "*andsi3_cconly", "*andsi3_zarch", "*iorsi3_cc",
"*iorsi3_cconly", "*iorsi3_zarch", "*xorsi3_cc", "*xorsi3_cconly",
"*xorsi3", "*xorhi3", "*xorqi3"): Added instruction using extended
immediates.
("extend<mode>di2", "extend<mode>si2", "zero_extend<mode>di2",
"zero_extend<mode>si2"): Allow memory operands and don't manually emit
insns for TARGET_EXTIMM.
Index: gcc/config.gcc
===================================================================
--- gcc/config.gcc.orig 2005-08-16 16:32:17.000000000 +0200
+++ gcc/config.gcc 2005-08-16 16:34:34.000000000 +0200
@@ -2657,7 +2657,7 @@ case "${target}" in
for which in arch tune; do
eval "val=\$with_$which"
case ${val} in
- "" | g5 | g6 | z900 | z990)
+ "" | g5 | g6 | z900 | z990 | z9-109)
# OK
;;
*)
Index: gcc/config/s390/2084.md
===================================================================
--- gcc/config/s390/2084.md.orig 2005-08-16 16:32:17.000000000 +0200
+++ gcc/config/s390/2084.md 2005-08-16 16:34:34.000000000 +0200
@@ -62,69 +62,69 @@
;;
(define_insn_reservation "x_int" 1
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(and (eq_attr "type" "integer")
(eq_attr "atype" "reg")))
"x-e1-st,x-wr-st")
(define_insn_reservation "x_agen" 1
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(and (eq_attr "type" "integer")
(eq_attr "atype" "agen")))
"x-e1-st,x-wr-st")
(define_insn_reservation "x_lr" 1
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "lr"))
"x-e1-st,x-wr-st")
(define_insn_reservation "x_la" 1
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "la"))
"x-e1-st,x-wr-st")
(define_insn_reservation "x_larl" 1
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "larl"))
"x-e1-st,x-wr-st")
(define_insn_reservation "x_load" 1
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "load"))
"x-e1-st+x-mem,x-wr-st")
(define_insn_reservation "x_store" 1
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "store"))
"x-e1-st+x_store_tok,x-wr-st")
(define_insn_reservation "x_branch" 1
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "branch"))
"x_e1_r,x_wr_r")
(define_insn_reservation "x_call" 5
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "jsr"))
"x-e1-np*5,x-wr-np")
(define_insn_reservation "x_mul_hi" 2
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "imulhi"))
"x-e1-np*2,x-wr-np")
(define_insn_reservation "x_mul_sidi" 4
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "imulsi,imuldi"))
"x-e1-np*4,x-wr-np")
(define_insn_reservation "x_div" 10
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "idiv"))
"x-e1-np*10,x-wr-np")
(define_insn_reservation "x_sem" 17
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "sem"))
"x-e1-np+x-mem,x-e1-np*16,x-wr-st")
@@ -133,27 +133,27 @@
;;
(define_insn_reservation "x_cs" 1
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "cs"))
"x-e1-np,x-wr-np")
(define_insn_reservation "x_vs" 1
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "vs"))
"x-e1-np*10,x-wr-np")
(define_insn_reservation "x_stm" 1
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "stm"))
"(x-e1-np+x_store_tok)*10,x-wr-np")
(define_insn_reservation "x_lm" 1
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "lm"))
"x-e1-np*10,x-wr-np")
(define_insn_reservation "x_other" 1
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "other"))
"x-e1-np,x-wr-np")
@@ -162,52 +162,52 @@
;;
(define_insn_reservation "x_fsimpdf" 6
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "fsimpdf,fmuldf"))
"x_e1_t,x-wr-fp")
(define_insn_reservation "x_fsimpsf" 6
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "fsimpsf,fmulsf"))
"x_e1_t,x-wr-fp")
(define_insn_reservation "x_fdivdf" 36
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "fdivdf,fsqrtdf"))
"x_e1_t*30,x-wr-fp")
(define_insn_reservation "x_fdivsf" 36
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "fdivsf,fsqrtsf"))
"x_e1_t*30,x-wr-fp")
(define_insn_reservation "x_floaddf" 6
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "floaddf"))
"x_e1_t,x-wr-fp")
(define_insn_reservation "x_floadsf" 6
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "floadsf"))
"x_e1_t,x-wr-fp")
(define_insn_reservation "x_fstoredf" 1
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "fstoredf"))
"x_e1_t,x-wr-fp")
(define_insn_reservation "x_fstoresf" 1
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "fstoresf"))
"x_e1_t,x-wr-fp")
(define_insn_reservation "x_ftoi" 1
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "ftoi"))
"x_e1_t*3,x-wr-fp")
(define_insn_reservation "x_itof" 7
- (and (eq_attr "cpu" "z990")
+ (and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "itof"))
"x_e1_t*3,x-wr-fp")
Index: gcc/config/s390/s390.c
===================================================================
--- gcc/config/s390/s390.c.orig 2005-08-16 16:32:17.000000000 +0200
+++ gcc/config/s390/s390.c 2005-08-16 16:34:34.000000000 +0200
@@ -153,6 +153,36 @@ struct processor_costs z990_cost =
COSTS_N_INSNS (31), /* DSGR */
};
+static const
+struct processor_costs z9_109_cost =
+{
+ COSTS_N_INSNS (4), /* M */
+ COSTS_N_INSNS (2), /* MGHI */
+ COSTS_N_INSNS (2), /* MH */
+ COSTS_N_INSNS (2), /* MHI */
+ COSTS_N_INSNS (4), /* ML */
+ COSTS_N_INSNS (4), /* MR */
+ COSTS_N_INSNS (5), /* MS */
+ COSTS_N_INSNS (6), /* MSG */
+ COSTS_N_INSNS (4), /* MSGF */
+ COSTS_N_INSNS (4), /* MSGFR */
+ COSTS_N_INSNS (4), /* MSGR */
+ COSTS_N_INSNS (4), /* MSR */
+ COSTS_N_INSNS (1), /* multiplication in DFmode */
+ COSTS_N_INSNS (66), /* SQDBR */
+ COSTS_N_INSNS (38), /* SQEBR */
+ COSTS_N_INSNS (1), /* MADBR */
+ COSTS_N_INSNS (1), /* MAEBR */
+ COSTS_N_INSNS (40), /* DDBR */
+ COSTS_N_INSNS (37), /* DDR */
+ COSTS_N_INSNS (26), /* DDBR */
+ COSTS_N_INSNS (28), /* DER */
+ COSTS_N_INSNS (30), /* DLGR */
+ COSTS_N_INSNS (23), /* DLR */
+ COSTS_N_INSNS (23), /* DR */
+ COSTS_N_INSNS (24), /* DSGFR */
+ COSTS_N_INSNS (24), /* DSGR */
+};
extern int reload_completed;
@@ -272,6 +302,12 @@ struct machine_function GTY(())
CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
#define CONST_OK_FOR_K(x) \
CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
+#define CONST_OK_FOR_Os(x) \
+ CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
+#define CONST_OK_FOR_Op(x) \
+ CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
+#define CONST_OK_FOR_On(x) \
+ CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
/* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
@@ -1207,6 +1243,8 @@ s390_handle_arch_option (const char *arg
{"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
{"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
| PF_LONG_DISPLACEMENT},
+ {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
+ | PF_LONG_DISPLACEMENT | PF_EXTIMM},
};
size_t i;
@@ -1293,14 +1331,14 @@ override_options (void)
if (TARGET_64BIT && !TARGET_ZARCH)
error ("64-bit ABI not supported in ESA/390 mode");
-
/* Set processor cost function. */
- if (s390_tune == PROCESSOR_2084_Z990)
+ if (s390_tune == PROCESSOR_2094_Z9_109)
+ s390_cost = &z9_109_cost;
+ else if (s390_tune == PROCESSOR_2084_Z990)
s390_cost = &z990_cost;
else
s390_cost = &z900_cost;
-
-
+
if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
error ("-mbackchain -mpacked-stack -mhard-float are not supported "
"in combination");
@@ -1876,6 +1914,28 @@ s390_const_ok_for_constraint_p (HOST_WID
break;
+ case 'O':
+ if (!TARGET_EXTIMM)
+ return 0;
+
+ switch (str[1])
+ {
+ case 's':
+ return trunc_int_for_mode (value, SImode) == value;
+
+ case 'p':
+ return value == 0
+ || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
+
+ case 'n':
+ return value == -1
+ || s390_single_part (GEN_INT (value), DImode, SImode, -1) == 1;
+
+ default:
+ gcc_unreachable ();
+ }
+ break;
+
case 'P':
return legitimate_reload_constant_p (GEN_INT (value));
@@ -2307,9 +2367,9 @@ legitimate_reload_constant_p (rtx op)
&& DISP_IN_RANGE (INTVAL (op)))
return true;
- /* Accept l(g)hi operands. */
+ /* Accept l(g)hi/l(g)fi operands. */
if (GET_CODE (op) == CONST_INT
- && CONST_OK_FOR_K (INTVAL (op)))
+ && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
return true;
/* Accept lliXX operands. */
@@ -2319,6 +2379,12 @@ legitimate_reload_constant_p (rtx op)
&& s390_single_part (op, word_mode, HImode, 0) >= 0)
return true;
+ if (TARGET_EXTIMM
+ && GET_CODE (op) == CONST_INT
+ && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
+ && s390_single_part (op, word_mode, SImode, 0) >= 0)
+ return true;
+
/* Accept larl operands. */
if (TARGET_CPU_ZARCH
&& larl_operand (op, VOIDmode))
@@ -4115,6 +4181,14 @@ print_operand (FILE *file, rtx x, int co
else if (code == 'j')
fprintf (file, HOST_WIDE_INT_PRINT_DEC,
s390_extract_part (x, HImode, -1));
+ else if (code == 'k')
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC,
+ s390_extract_part (x, SImode, 0));
+ else if (code == 'm')
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC,
+ s390_extract_part (x, SImode, -1));
+ else if (code == 'o')
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
else
fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
break;
@@ -4270,7 +4344,8 @@ s390_adjust_priority (rtx insn ATTRIBUTE
if (! INSN_P (insn))
return priority;
- if (s390_tune != PROCESSOR_2084_Z990)
+ if (s390_tune != PROCESSOR_2084_Z990
+ && s390_tune != PROCESSOR_2094_Z9_109)
return priority;
switch (s390_safe_attr_type (insn))
@@ -4294,7 +4369,8 @@ s390_adjust_priority (rtx insn ATTRIBUTE
static int
s390_issue_rate (void)
{
- if (s390_tune == PROCESSOR_2084_Z990)
+ if (s390_tune == PROCESSOR_2084_Z990
+ || s390_tune == PROCESSOR_2094_Z9_109)
return 3;
return 1;
}
@@ -7717,9 +7793,11 @@ s390_output_mi_thunk (FILE *file, tree t
{
/* Setup literal pool pointer if required. */
if ((!DISP_IN_RANGE (delta)
- && !CONST_OK_FOR_K (delta))
+ && !CONST_OK_FOR_K (delta)
+ && !CONST_OK_FOR_Os (delta))
|| (!DISP_IN_RANGE (vcall_offset)
- && !CONST_OK_FOR_K (vcall_offset)))
+ && !CONST_OK_FOR_K (vcall_offset)
+ && !CONST_OK_FOR_Os (vcall_offset)))
{
op[5] = gen_label_rtx ();
output_asm_insn ("larl\t%4,%5", op);
@@ -7734,6 +7812,8 @@ s390_output_mi_thunk (FILE *file, tree t
output_asm_insn ("lay\t%1,%2(%1)", op);
else if (CONST_OK_FOR_K (delta))
output_asm_insn ("aghi\t%1,%2", op);
+ else if (CONST_OK_FOR_Os (delta))
+ output_asm_insn ("agfi\t%1,%2", op);
else
{
op[6] = gen_label_rtx ();
@@ -7755,6 +7835,12 @@ s390_output_mi_thunk (FILE *file, tree t
output_asm_insn ("ag\t%4,0(%1)", op);
output_asm_insn ("ag\t%1,0(%4)", op);
}
+ else if (CONST_OK_FOR_Os (vcall_offset))
+ {
+ output_asm_insn ("lgfi\t%4,%3", op);
+ output_asm_insn ("ag\t%4,0(%1)", op);
+ output_asm_insn ("ag\t%1,0(%4)", op);
+ }
else
{
op[7] = gen_label_rtx ();
@@ -7792,9 +7878,11 @@ s390_output_mi_thunk (FILE *file, tree t
/* Setup base pointer if required. */
if (!vcall_offset
|| (!DISP_IN_RANGE (delta)
- && !CONST_OK_FOR_K (delta))
+ && !CONST_OK_FOR_K (delta)
+ && !CONST_OK_FOR_Os (delta))
|| (!DISP_IN_RANGE (delta)
- && !CONST_OK_FOR_K (vcall_offset)))
+ && !CONST_OK_FOR_K (vcall_offset)
+ && !CONST_OK_FOR_Os (vcall_offset)))
{
op[5] = gen_label_rtx ();
output_asm_insn ("basr\t%4,0", op);
@@ -7811,6 +7899,8 @@ s390_output_mi_thunk (FILE *file, tree t
output_asm_insn ("lay\t%1,%2(%1)", op);
else if (CONST_OK_FOR_K (delta))
output_asm_insn ("ahi\t%1,%2", op);
+ else if (CONST_OK_FOR_Os (delta))
+ output_asm_insn ("afi\t%1,%2", op);
else
{
op[6] = gen_label_rtx ();
@@ -7837,6 +7927,12 @@ s390_output_mi_thunk (FILE *file, tree t
output_asm_insn ("a\t%4,0(%1)", op);
output_asm_insn ("a\t%1,0(%4)", op);
}
+ else if (CONST_OK_FOR_Os (vcall_offset))
+ {
+ output_asm_insn ("iilf\t%4,%3", op);
+ output_asm_insn ("a\t%4,0(%1)", op);
+ output_asm_insn ("a\t%1,0(%4)", op);
+ }
else
{
op[7] = gen_label_rtx ();
Index: gcc/config/s390/s390.h
===================================================================
--- gcc/config/s390/s390.h.orig 2005-08-16 16:32:17.000000000 +0200
+++ gcc/config/s390/s390.h 2005-08-16 16:34:34.000000000 +0200
@@ -40,6 +40,7 @@ enum processor_type
PROCESSOR_9672_G6,
PROCESSOR_2064_Z900,
PROCESSOR_2084_Z990,
+ PROCESSOR_2094_Z9_109,
PROCESSOR_max
};
@@ -49,7 +50,8 @@ enum processor_flags
{
PF_IEEE_FLOAT = 1,
PF_ZARCH = 2,
- PF_LONG_DISPLACEMENT = 4
+ PF_LONG_DISPLACEMENT = 4,
+ PF_EXTIMM = 8
};
extern enum processor_type s390_tune;
@@ -64,10 +66,13 @@ extern enum processor_flags s390_arch_fl
(s390_arch_flags & PF_ZARCH)
#define TARGET_CPU_LONG_DISPLACEMENT \
(s390_arch_flags & PF_LONG_DISPLACEMENT)
+#define TARGET_CPU_EXTIMM \
+ (s390_arch_flags & PF_EXTIMM)
#define TARGET_LONG_DISPLACEMENT \
(TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT)
-
+#define TARGET_EXTIMM \
+ (TARGET_ZARCH && TARGET_CPU_EXTIMM)
/* Run-time target specification. */
@@ -501,7 +506,8 @@ extern const enum reg_class regclass_map
((C) == 'U' || (C) == 'W' || (C) == 'Y')
#define CONSTRAINT_LEN(C, STR) \
- ((C) == 'N' ? 5 : \
+ ((C) == 'N' ? 5 : \
+ (C) == 'O' ? 2 : \
(C) == 'A' ? 2 : \
(C) == 'B' ? 2 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
@@ -980,6 +986,9 @@ do { \
indexing purposes) so give the MEM rtx a byte's mode. */
#define FUNCTION_MODE QImode
+/* Specify the value which is used when clz operand is zero. */
+#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1)
+
/* Machine-specific symbol_ref flags. */
#define SYMBOL_FLAG_ALIGN1 (SYMBOL_FLAG_MACH_DEP << 0)
Index: gcc/config/s390/s390.md
===================================================================
--- gcc/config/s390/s390.md.orig 2005-08-16 16:32:17.000000000 +0200
+++ gcc/config/s390/s390.md 2005-08-17 10:42:09.000000000 +0200
@@ -47,6 +47,12 @@
;; has a value different from its other parts. If the letter x
;; is specified instead of a part number, the constraint matches
;; if there is any single part with non-default value.
+;; O -- Multiple letter constraint followed by 1 parameter.
+;; s: Signed extended immediate value (-2G .. 2G-1).
+;; p: Positive extended immediate value (0 .. 4G-1).
+;; n: Negative extended immediate value (-4G .. -1).
+;; These constraints do not accept any operand if the machine does
+;; not provide the extended-immediate facility.
;; P -- Any integer constant that can be loaded without literal pool.
;; Q -- Memory reference without index register and with short displacement.
;; R -- Memory reference with index register and short displacement.
@@ -249,7 +255,7 @@
;; distinguish between g5 and g6, but there are differences between the two
;; CPUs could in theory be modeled.
-(define_attr "cpu" "g5,g6,z900,z990"
+(define_attr "cpu" "g5,g6,z900,z990,z9_109"
(const (symbol_ref "s390_tune")))
;; Pipeline description for z900. For lack of anything better,
@@ -438,13 +444,36 @@
"ltgfr\t%2,%0"
[(set_attr "op_type" "RRE")])
+(define_insn "*tstdi_extimm"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:DI 0 "nonimmediate_operand" "d,m")
+ (match_operand:DI 1 "const0_operand" "")))
+ (set (match_operand:DI 2 "register_operand" "=d,d")
+ (match_dup 0))]
+ "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && TARGET_EXTIMM"
+ "@
+ ltgr\t%2,%0
+ ltg\t%2,%0"
+ [(set_attr "op_type" "RRE,RXY")])
+
+(define_insn "*tstdi_cconly_extimm"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:DI 0 "nonimmediate_operand" "d,m")
+ (match_operand:DI 1 "const0_operand" "")))
+ (clobber (match_scratch:DI 2 "=X,d"))]
+ "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && TARGET_EXTIMM"
+ "@
+ ltgr\t%0,%0
+ ltg\t%2,%0"
+ [(set_attr "op_type" "RRE,RXY")])
+
(define_insn "*tstdi"
[(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "register_operand" "d")
(match_operand:DI 1 "const0_operand" "")))
(set (match_operand:DI 2 "register_operand" "=d")
(match_dup 0))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
+ "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
"ltgr\t%2,%0"
[(set_attr "op_type" "RRE")])
@@ -465,6 +494,28 @@
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
+(define_insn "*tstsi_extimm"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:SI 0 "nonimmediate_operand" "d,m")
+ (match_operand:SI 1 "const0_operand" "")))
+ (set (match_operand:SI 2 "register_operand" "=d,d")
+ (match_dup 0))]
+ "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
+ "@
+ ltr\t%2,%0
+ lt\t%2,%0"
+ [(set_attr "op_type" "RR,RXY")])
+
+(define_insn "*tstsi_cconly_extimm"
+ [(set (reg CC_REGNUM)
+ (compare (match_operand:SI 0 "nonimmediate_operand" "d,m")
+ (match_operand:SI 1 "const0_operand" "")))
+ (clobber (match_scratch:SI 2 "=X,d"))]
+ "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
+ "@
+ ltr\t%0,%0
+ lt\t%2,%0"
+ [(set_attr "op_type" "RR,RXY")])
(define_insn "*tstsi"
[(set (reg CC_REGNUM)
@@ -472,7 +523,7 @@
(match_operand:SI 1 "const0_operand" "")))
(set (match_operand:SI 2 "register_operand" "=d,d,d")
(match_dup 0))]
- "s390_match_ccmode(insn, CCSmode)"
+ "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
"@
ltr\t%2,%0
icm\t%2,15,%S0
@@ -563,28 +614,30 @@
(define_insn "*cmpdi_cct"
[(set (reg CC_REGNUM)
- (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,Q")
- (match_operand:DI 1 "general_operand" "d,K,m,BQ")))]
+ (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
+ (match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))]
"s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
"@
cgr\t%0,%1
cghi\t%0,%h1
+ cgfi\t%0,%1
cg\t%0,%1
#"
- [(set_attr "op_type" "RRE,RI,RXY,SS")])
+ [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")])
(define_insn "*cmpsi_cct"
[(set (reg CC_REGNUM)
- (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,Q")
- (match_operand:SI 1 "general_operand" "d,K,R,T,BQ")))]
+ (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
+ (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
"s390_match_ccmode (insn, CCTmode)"
"@
cr\t%0,%1
chi\t%0,%h1
+ cfi\t%0,%1
c\t%0,%1
cy\t%0,%1
#"
- [(set_attr "op_type" "RR,RI,RX,RXY,SS")])
+ [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")])
; Compare (signed) instructions
@@ -601,14 +654,15 @@
(define_insn "*cmpdi_ccs"
[(set (reg CC_REGNUM)
- (compare (match_operand:DI 0 "register_operand" "d,d,d")
- (match_operand:DI 1 "general_operand" "d,K,m")))]
+ (compare (match_operand:DI 0 "register_operand" "d,d,d,d")
+ (match_operand:DI 1 "general_operand" "d,K,Os,m")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
"@
cgr\t%0,%1
cghi\t%0,%h1
+ cgfi\t%0,%1
cg\t%0,%1"
- [(set_attr "op_type" "RRE,RI,RXY")])
+ [(set_attr "op_type" "RRE,RI,RIL,RXY")])
(define_insn "*cmpsi_ccs_sign"
[(set (reg CC_REGNUM)
@@ -622,15 +676,16 @@
(define_insn "*cmpsi_ccs"
[(set (reg CC_REGNUM)
- (compare (match_operand:SI 0 "register_operand" "d,d,d,d")
- (match_operand:SI 1 "general_operand" "d,K,R,T")))]
+ (compare (match_operand:SI 0 "register_operand" "d,d,d,d,d")
+ (match_operand:SI 1 "general_operand" "d,K,Os,R,T")))]
"s390_match_ccmode(insn, CCSmode)"
"@
cr\t%0,%1
chi\t%0,%h1
+ cfi\t%0,%1
c\t%0,%1
cy\t%0,%1"
- [(set_attr "op_type" "RR,RI,RX,RXY")])
+ [(set_attr "op_type" "RR,RI,RIL,RX,RXY")])
; Compare (unsigned) instructions
@@ -647,28 +702,30 @@
(define_insn "*cmpdi_ccu"
[(set (reg CC_REGNUM)
- (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q,BQ")
- (match_operand:DI 1 "general_operand" "d,m,BQ,Q")))]
+ (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
+ (match_operand:DI 1 "general_operand" "d,Op,m,BQ,Q")))]
"s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
"@
clgr\t%0,%1
+ clgfi\t%0,%1
clg\t%0,%1
#
#"
- [(set_attr "op_type" "RRE,RXY,SS,SS")])
+ [(set_attr "op_type" "RRE,RIL,RXY,SS,SS")])
(define_insn "*cmpsi_ccu"
[(set (reg CC_REGNUM)
- (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
- (match_operand:SI 1 "general_operand" "d,R,T,BQ,Q")))]
+ (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,Q,BQ")
+ (match_operand:SI 1 "general_operand" "d,Os,R,T,BQ,Q")))]
"s390_match_ccmode (insn, CCUmode)"
"@
clr\t%0,%1
+ clfi\t%0,%o1
cl\t%0,%1
cly\t%0,%1
#
#"
- [(set_attr "op_type" "RR,RX,RXY,SS,SS")])
+ [(set_attr "op_type" "RR,RIL,RX,RXY,SS,SS")])
(define_insn "*cmphi_ccu"
[(set (reg CC_REGNUM)
@@ -873,12 +930,46 @@
[(set_attr "op_type" "RIL")
(set_attr "type" "larl")])
+(define_insn "*movdi_64extimm"
+ [(set (match_operand:DI 0 "nonimmediate_operand"
+ "=d,d,d,d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
+ (match_operand:DI 1 "general_operand"
+ "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
+ "TARGET_64BIT && TARGET_EXTIMM"
+ "@
+ lghi\t%0,%h1
+ llihh\t%0,%i1
+ llihl\t%0,%i1
+ llilh\t%0,%i1
+ llill\t%0,%i1
+ lgfi\t%0,%1
+ llihf\t%0,%k1
+ llilf\t%0,%k1
+ lay\t%0,%a1
+ lgr\t%0,%1
+ lg\t%0,%1
+ stg\t%1,%0
+ ldr\t%0,%1
+ ld\t%0,%1
+ ldy\t%0,%1
+ std\t%1,%0
+ stdy\t%1,%0
+ #
+ #
+ stam\t%1,%N1,%S0
+ lam\t%0,%N0,%S1
+ #"
+ [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RXY,RRE,RXY,RXY,
+ RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
+ (set_attr "type" "*,*,*,*,*,*,*,*,la,lr,load,store,
+ floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
+
(define_insn "*movdi_64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
(match_operand:DI 1 "general_operand"
"K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
- "TARGET_64BIT"
+ "TARGET_64BIT && !TARGET_EXTIMM"
"@
lghi\t%0,%h1
llihh\t%0,%i1
@@ -1092,14 +1183,15 @@
(define_insn "*movsi_zarch"
[(set (match_operand:SI 0 "nonimmediate_operand"
- "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
+ "=d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
(match_operand:SI 1 "general_operand"
- "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
+ "K,N0HS0,N1HS0,Os,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
"TARGET_ZARCH"
"@
lhi\t%0,%h1
llilh\t%0,%i1
llill\t%0,%i1
+ iilf\t%0,%o1
lay\t%0,%a1
lr\t%0,%1
l\t%0,%1
@@ -1116,9 +1208,9 @@
stam\t%1,%1,%S0
lam\t%0,%0,%S1
#"
- [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,
+ [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RR,RX,RXY,RX,RXY,
RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
- (set_attr "type" "*,*,*,la,lr,load,load,store,store,
+ (set_attr "type" "*,*,*,*,la,lr,load,load,store,store,
floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
(define_insn "*movsi_esa"
@@ -2385,7 +2477,6 @@
[(set (match_operand:DI 0 "register_operand" "")
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
""
- "
{
if (!TARGET_64BIT)
{
@@ -2395,8 +2486,7 @@
emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
DONE;
}
-}
-")
+})
(define_insn "*extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -2413,9 +2503,8 @@
(define_expand "extend<mode>di2"
[(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:HQI 1 "register_operand" "")))]
+ (sign_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
""
- "
{
if (!TARGET_64BIT)
{
@@ -2424,7 +2513,7 @@
emit_insn (gen_extendsidi2 (operands[0], tmp));
DONE;
}
- else
+ else if (!TARGET_EXTIMM)
{
rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) -
GET_MODE_BITSIZE (<MODE>mode));
@@ -2433,8 +2522,16 @@
emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount));
DONE;
}
-}
-")
+})
+
+(define_insn "*extendhidi2_extimm"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
+ "TARGET_64BIT && TARGET_EXTIMM"
+ "@
+ lghr\t%0,%1
+ lgh\t%0,%1"
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*extendhidi2"
[(set (match_operand:DI 0 "register_operand" "=d")
@@ -2443,6 +2540,15 @@
"lgh\t%0,%1"
[(set_attr "op_type" "RXY")])
+(define_insn "*extendqidi2_extimm"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
+ "TARGET_64BIT && TARGET_EXTIMM"
+ "@
+ lgbr\t%0,%1
+ lgb\t%0,%1"
+ [(set_attr "op_type" "RRE,RXY")])
+
(define_insn "*extendqidi2"
[(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
@@ -2471,32 +2577,52 @@
(define_expand "extend<mode>si2"
[(set (match_operand:SI 0 "register_operand" "")
- (sign_extend:SI (match_operand:HQI 1 "register_operand" "")))]
+ (sign_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
""
- "
{
- rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) -
- GET_MODE_BITSIZE(<MODE>mode));
- operands[1] = gen_lowpart (SImode, operands[1]);
- emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount));
- emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount));
- DONE;
-}
-")
+ if (!TARGET_EXTIMM)
+ {
+ rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) -
+ GET_MODE_BITSIZE(<MODE>mode));
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount));
+ emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount));
+ DONE;
+ }
+})
+
+(define_insn "*extendhisi2_extimm"
+ [(set (match_operand:SI 0 "register_operand" "=d,d,d")
+ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))]
+ "TARGET_EXTIMM"
+ "@
+ lhr\t%0,%1
+ lh\t%0,%1
+ lhy\t%0,%1"
+ [(set_attr "op_type" "RRE,RX,RXY")])
(define_insn "*extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=d,d")
(sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
- ""
+ "!TARGET_EXTIMM"
"@
lh\t%0,%1
lhy\t%0,%1"
[(set_attr "op_type" "RX,RXY")])
+(define_insn "*extendqisi2_extimm"
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
+ "TARGET_EXTIMM"
+ "@
+ lbr\t%0,%1
+ lb\t%0,%1"
+ [(set_attr "op_type" "RRE,RXY")])
+
(define_insn "*extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=d")
(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
- "TARGET_LONG_DISPLACEMENT"
+ "TARGET_LONG_DISPLACEMENT && !TARGET_EXTIMM"
"lb\t%0,%1"
[(set_attr "op_type" "RXY")])
@@ -2528,7 +2654,6 @@
[(set (match_operand:DI 0 "register_operand" "")
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
""
- "
{
if (!TARGET_64BIT)
{
@@ -2537,8 +2662,7 @@
emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
DONE;
}
-}
-")
+})
(define_insn "*zero_extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -2555,9 +2679,8 @@
(define_expand "zero_extend<mode>di2"
[(set (match_operand:DI 0 "register_operand" "")
- (zero_extend:DI (match_operand:HQI 1 "register_operand" "")))]
+ (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
""
- "
{
if (!TARGET_64BIT)
{
@@ -2566,7 +2689,7 @@
emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
DONE;
}
- else
+ else if (!TARGET_EXTIMM)
{
rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
GET_MODE_BITSIZE(<MODE>mode));
@@ -2575,13 +2698,21 @@
emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
DONE;
}
-}
-")
+})
+
+(define_insn "*zero_extend<mode>di2_extimm"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
+ "TARGET_64BIT && TARGET_EXTIMM"
+ "@
+ llg<hc>r\t%0,%1
+ llg<hc>\t%0,%1"
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*zero_extend<mode>di2"
[(set (match_operand:DI 0 "register_operand" "=d")
(zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))]
- "TARGET_64BIT"
+ "TARGET_64BIT && !TARGET_EXTIMM"
"llg<hc>\t%0,%1"
[(set_attr "op_type" "RXY")])
@@ -2647,21 +2778,31 @@
(define_expand "zero_extend<mode>si2"
[(set (match_operand:SI 0 "register_operand" "")
- (zero_extend:SI (match_operand:HQI 1 "register_operand" "")))]
+ (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
""
- "
{
- operands[1] = gen_lowpart (SImode, operands[1]);
- emit_insn (gen_andsi3 (operands[0], operands[1],
- GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
- DONE;
+ if (!TARGET_EXTIMM)
+ {
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ emit_insn (gen_andsi3 (operands[0], operands[1],
+ GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
+ DONE;
}
-")
+})
+
+(define_insn "*zero_extend<mode>si2_extimm"
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
+ "TARGET_EXTIMM"
+ "@
+ ll<hc>r\t%0,%1
+ ll<hc>\t%0,%1"
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*zero_extend<mode>si2_64"
[(set (match_operand:SI 0 "register_operand" "=d")
(zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))]
- "TARGET_ZARCH"
+ "TARGET_ZARCH && !TARGET_EXTIMM"
"llg<hc>\t%0,%1"
[(set_attr "op_type" "RXY")])
@@ -2695,19 +2836,17 @@
(define_expand "zero_extendqihi2"
[(set (match_operand:HI 0 "register_operand" "")
(zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
- "TARGET_ZARCH"
- "
+ "TARGET_ZARCH && !TARGET_EXTIMM"
{
operands[1] = gen_lowpart (HImode, operands[1]);
emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
DONE;
-}
-")
+})
(define_insn "*zero_extendqihi2_64"
[(set (match_operand:HI 0 "register_operand" "=d")
(zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
- "TARGET_ZARCH"
+ "TARGET_ZARCH && !TARGET_EXTIMM"
"llgc\t%0,%1"
[(set_attr "op_type" "RXY")])
@@ -3090,29 +3229,34 @@
(define_insn "*adddi3_imm_cc"
[(set (reg CC_REGNUM)
- (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
- (match_operand:DI 2 "const_int_operand" "K"))
+ (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
+ (match_operand:DI 2 "const_int_operand" "K,Os"))
(const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d")
+ (set (match_operand:DI 0 "register_operand" "=d,d")
(plus:DI (match_dup 1) (match_dup 2)))]
"TARGET_64BIT
&& s390_match_ccmode (insn, CCAmode)
- && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
- "aghi\t%0,%h2"
- [(set_attr "op_type" "RI")])
+ && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
+ || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))"
+ "@
+ aghi\t%0,%h2
+ agfi\t%0,%2"
+ [(set_attr "op_type" "RI,RIL")])
(define_insn "*adddi3_carry1_cc"
[(set (reg CC_REGNUM)
- (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
+ (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:DI 2 "general_operand" "d,Op,On,m"))
(match_dup 1)))
- (set (match_operand:DI 0 "register_operand" "=d,d")
+ (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
(plus:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
"@
algr\t%0,%2
+ algfi\t%0,%2
+ slgfi\t%0,%n2
alg\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
+ [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
(define_insn "*adddi3_carry1_cconly"
[(set (reg CC_REGNUM)
@@ -3128,16 +3272,18 @@
(define_insn "*adddi3_carry2_cc"
[(set (reg CC_REGNUM)
- (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
+ (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:DI 2 "general_operand" "d,Op,On,m"))
(match_dup 2)))
- (set (match_operand:DI 0 "register_operand" "=d,d")
+ (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
(plus:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
"@
algr\t%0,%2
+ algfi\t%0,%2
+ slgfi\t%0,%n2
alg\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
+ [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
(define_insn "*adddi3_carry2_cconly"
[(set (reg CC_REGNUM)
@@ -3153,16 +3299,18 @@
(define_insn "*adddi3_cc"
[(set (reg CC_REGNUM)
- (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,m"))
+ (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:DI 2 "general_operand" "d,Op,On,m"))
(const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d,d")
+ (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
(plus:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
algr\t%0,%2
+ algfi\t%0,%2
+ slgfi\t%0,%n2
alg\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
+ [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
(define_insn "*adddi3_cconly"
[(set (reg CC_REGNUM)
@@ -3188,16 +3336,18 @@
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_64"
- [(set (match_operand:DI 0 "register_operand" "=d,d,d")
- (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:DI 2 "general_operand" "d,K,m") ) )
+ [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d")
+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0")
+ (match_operand:DI 2 "general_operand" "d,K,Op,On,m") ) )
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"@
agr\t%0,%2
aghi\t%0,%h2
+ algfi\t%0,%2
+ slgfi\t%0,%n2
ag\t%0,%2"
- [(set_attr "op_type" "RRE,RI,RXY")])
+ [(set_attr "op_type" "RRE,RI,RIL,RIL,RXY")])
(define_insn_and_split "*adddi3_31z"
[(set (match_operand:DI 0 "register_operand" "=&d")
@@ -3270,29 +3420,34 @@
(define_insn "*addsi3_imm_cc"
[(set (reg CC_REGNUM)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:SI 2 "const_int_operand" "K"))
+ (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
+ (match_operand:SI 2 "const_int_operand" "K,Os"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d")
+ (set (match_operand:SI 0 "register_operand" "=d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCAmode)
- && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
- "ahi\t%0,%h2"
- [(set_attr "op_type" "RI")])
+ && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
+ || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))
+ && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << 31)"
+ "@
+ ahi\t%0,%h2
+ afi\t%0,%2"
+ [(set_attr "op_type" "RI,RIL")])
(define_insn "*addsi3_carry1_cc"
[(set (reg CC_REGNUM)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,T"))
+ (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:SI 2 "general_operand" "d,Os,R,T"))
(match_dup 1)))
- (set (match_operand:SI 0 "register_operand" "=d,d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\t%0,%2
+ alfi\t%0,%o2
al\t%0,%2
aly\t%0,%2"
- [(set_attr "op_type" "RR,RX,RXY")])
+ [(set_attr "op_type" "RR,RIL,RX,RXY")])
(define_insn "*addsi3_carry1_cconly"
[(set (reg CC_REGNUM)
@@ -3309,17 +3464,18 @@
(define_insn "*addsi3_carry2_cc"
[(set (reg CC_REGNUM)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,T"))
+ (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:SI 2 "general_operand" "d,Os,R,T"))
(match_dup 2)))
- (set (match_operand:SI 0 "register_operand" "=d,d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\t%0,%2
+ alfi\t%0,%o2
al\t%0,%2
aly\t%0,%2"
- [(set_attr "op_type" "RR,RX,RXY")])
+ [(set_attr "op_type" "RR,RIL,RX,RXY")])
(define_insn "*addsi3_carry2_cconly"
[(set (reg CC_REGNUM)
@@ -3336,17 +3492,18 @@
(define_insn "*addsi3_cc"
[(set (reg CC_REGNUM)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,T"))
+ (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:SI 2 "general_operand" "d,Os,R,T"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode)"
"@
alr\t%0,%2
+ alfi\t%0,%o2
al\t%0,%2
aly\t%0,%2"
- [(set_attr "op_type" "RR,RX,RXY")])
+ [(set_attr "op_type" "RR,RIL,RX,RXY")])
(define_insn "*addsi3_cconly"
[(set (reg CC_REGNUM)
@@ -3385,17 +3542,18 @@
[(set_attr "op_type" "RX,RXY")])
(define_insn "addsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
- (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:SI 2 "general_operand" "d,K,R,T")))
+ [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
+ (match_operand:SI 2 "general_operand" "d,K,Os,R,T")))
(clobber (reg:CC CC_REGNUM))]
""
"@
ar\t%0,%2
ahi\t%0,%h2
+ afi\t%0,%2
a\t%0,%2
ay\t%0,%2"
- [(set_attr "op_type" "RR,RI,RX,RXY")])
+ [(set_attr "op_type" "RR,RI,RIL,RX,RXY")])
;
; add(df|sf)3 instruction pattern(s).
@@ -4673,6 +4831,29 @@
ng\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
+(define_insn "*anddi3_extimm"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
+ (and:DI (match_operand:DI 1 "nonimmediate_operand"
+ "%d,o,0,0,0,0,0,0,0,0,0,0")
+ (match_operand:DI 2 "general_operand"
+ "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,m,NxQDF,Q")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
+ "@
+ #
+ #
+ nihh\t%0,%j2
+ nihl\t%0,%j2
+ nilh\t%0,%j2
+ nill\t%0,%j2
+ nihf\t%0,%m2
+ nilf\t%0,%m2
+ ngr\t%0,%2
+ ng\t%0,%2
+ #
+ #"
+ [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
+
(define_insn "*anddi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
(and:DI (match_operand:DI 1 "nonimmediate_operand"
@@ -4680,7 +4861,7 @@
(match_operand:DI 2 "general_operand"
"M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
+ "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
"@
#
#
@@ -4711,39 +4892,41 @@
(define_insn "*andsi3_cc"
[(set (reg CC_REGNUM)
- (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,T"))
+ (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:SI 2 "general_operand" "Os,d,R,T"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
(and:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
+ nilf\t%0,%o2
nr\t%0,%2
n\t%0,%2
ny\t%0,%2"
- [(set_attr "op_type" "RR,RX,RXY")])
+ [(set_attr "op_type" "RIL,RR,RX,RXY")])
(define_insn "*andsi3_cconly"
[(set (reg CC_REGNUM)
- (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,T"))
+ (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:SI 2 "general_operand" "Os,d,R,T"))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=d,d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d,d"))]
"s390_match_ccmode(insn, CCTmode)
/* Do not steal TM patterns. */
&& s390_single_part (operands[2], SImode, HImode, 0) < 0"
"@
+ nilf\t%0,%o2
nr\t%0,%2
n\t%0,%2
ny\t%0,%2"
- [(set_attr "op_type" "RR,RX,RXY")])
+ [(set_attr "op_type" "RIL,RR,RX,RXY")])
(define_insn "*andsi3_zarch"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,AQ,Q")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
(and:SI (match_operand:SI 1 "nonimmediate_operand"
- "%d,o,0,0,0,0,0,0,0")
+ "%d,o,0,0,0,0,0,0,0,0")
(match_operand:SI 2 "general_operand"
- "M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q")))
+ "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
@@ -4751,12 +4934,13 @@
#
nilh\t%0,%j2
nill\t%0,%j2
+ nilf\t%0,%o2
nr\t%0,%2
n\t%0,%2
ny\t%0,%2
#
#"
- [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY,SI,SS")])
+ [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")])
(define_insn "*andsi3_esa"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
@@ -4948,13 +5132,33 @@
og\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
+(define_insn "*iordi3_extimm"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
+ (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
+ (match_operand:DI 2 "general_operand"
+ "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,m,NxQD0,Q")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
+ "@
+ oihh\t%0,%i2
+ oihl\t%0,%i2
+ oilh\t%0,%i2
+ oill\t%0,%i2
+ oihf\t%0,%k2
+ oilf\t%0,%k2
+ ogr\t%0,%2
+ og\t%0,%2
+ #
+ #"
+ [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
+
(define_insn "*iordi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
(ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
(match_operand:DI 2 "general_operand"
"N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
+ "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
"@
oihh\t%0,%i2
oihl\t%0,%i2
@@ -4982,46 +5186,49 @@
(define_insn "*iorsi3_cc"
[(set (reg CC_REGNUM)
- (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,T"))
+ (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:SI 2 "general_operand" "Os,d,R,T"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
(ior:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
+ oilf\t%0,%o2
or\t%0,%2
o\t%0,%2
oy\t%0,%2"
- [(set_attr "op_type" "RR,RX,RXY")])
+ [(set_attr "op_type" "RIL,RR,RX,RXY")])
(define_insn "*iorsi3_cconly"
[(set (reg CC_REGNUM)
- (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,T"))
+ (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:SI 2 "general_operand" "Os,d,R,T"))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=d,d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d,d"))]
"s390_match_ccmode(insn, CCTmode)"
"@
+ oilf\t%0,%o2
or\t%0,%2
o\t%0,%2
oy\t%0,%2"
- [(set_attr "op_type" "RR,RX,RXY")])
+ [(set_attr "op_type" "RIL,RR,RX,RXY")])
(define_insn "*iorsi3_zarch"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q")
- (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
- (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q")))
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
+ (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
oilh\t%0,%i2
oill\t%0,%i2
+ oilf\t%0,%o2
or\t%0,%2
o\t%0,%2
oy\t%0,%2
#
#"
- [(set_attr "op_type" "RI,RI,RR,RX,RXY,SI,SS")])
+ [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")])
(define_insn "*iorsi3_esa"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
@@ -5213,12 +5420,27 @@
xr\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
+(define_insn "*xordi3_extimm"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
+ (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
+ (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,m,NxQD0,Q")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
+ "@
+ xihf\t%0,%k2
+ xilf\t%0,%k2
+ xgr\t%0,%2
+ xg\t%0,%2
+ #
+ #"
+ [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")])
+
(define_insn "*xordi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
(xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
+ "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
"@
xgr\t%0,%2
xg\t%0,%2
@@ -5242,44 +5464,47 @@
(define_insn "*xorsi3_cc"
[(set (reg CC_REGNUM)
- (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,T"))
+ (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:SI 2 "general_operand" "Os,d,R,T"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
(xor:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
+ xilf\t%0,%o2
xr\t%0,%2
x\t%0,%2
xy\t%0,%2"
- [(set_attr "op_type" "RR,RX,RXY")])
+ [(set_attr "op_type" "RIL,RR,RX,RXY")])
(define_insn "*xorsi3_cconly"
[(set (reg CC_REGNUM)
- (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,T"))
+ (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:SI 2 "general_operand" "Os,d,R,T"))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=d,d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d,d"))]
"s390_match_ccmode(insn, CCTmode)"
"@
+ xilf\t%0,%o2
xr\t%0,%2
x\t%0,%2
xy\t%0,%2"
- [(set_attr "op_type" "RR,RX,RXY")])
+ [(set_attr "op_type" "RIL,RR,RX,RXY")])
(define_insn "*xorsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q")
- (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q")))
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
+ (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
(clobber (reg:CC CC_REGNUM))]
"s390_logical_operator_ok_p (operands)"
"@
+ xilf\t%0,%o2
xr\t%0,%2
x\t%0,%2
xy\t%0,%2
#
#"
- [(set_attr "op_type" "RR,RX,RXY,SI,SS")])
+ [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")])
(define_split
[(set (match_operand:SI 0 "s_operand" "")
@@ -5296,16 +5521,17 @@
;
(define_insn "*xorhi3"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
- (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
(clobber (reg:CC CC_REGNUM))]
"s390_logical_operator_ok_p (operands)"
"@
+ xilf\t%0,%x2
xr\t%0,%2
#
#"
- [(set_attr "op_type" "RR,SI,SS")])
+ [(set_attr "op_type" "RIL,RR,SI,SS")])
(define_split
[(set (match_operand:HI 0 "s_operand" "")
@@ -5322,17 +5548,18 @@
;
(define_insn "*xorqi3"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q")
- (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:QI 2 "general_operand" "d,n,n,Q")))
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
+ (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
(clobber (reg:CC CC_REGNUM))]
"s390_logical_operator_ok_p (operands)"
"@
+ xilf\t%0,%b2
xr\t%0,%2
xi\t%S0,%b2
xiy\t%S0,%b2
#"
- [(set_attr "op_type" "RR,SI,SIY,SS")])
+ [(set_attr "op_type" "RIL,RR,SI,SIY,SS")])
;
; Block exclusive or (XC) patterns.
@@ -5801,6 +6028,49 @@
;;
+;; Find leftmost bit instructions.
+;;
+
+(define_expand "clzdi2"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (clz:DI (match_operand:DI 1 "register_operand" "d")))]
+ "TARGET_EXTIMM && TARGET_64BIT"
+{
+ rtx insn, clz_equal;
+ rtx wide_reg = gen_reg_rtx (TImode);
+ rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
+
+ clz_equal = gen_rtx_CLZ (DImode, operands[1]);
+
+ emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
+
+ insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
+ REG_NOTES (insn) =
+ gen_rtx_EXPR_LIST (REG_EQUAL, clz_equal, REG_NOTES (insn));
+
+ DONE;
+})
+
+(define_insn "clztidi2"
+ [(set (match_operand:TI 0 "register_operand" "=d")
+ (ior:TI
+ (ashift:TI
+ (zero_extend:TI
+ (xor:DI (match_operand:DI 1 "register_operand" "d")
+ (lshiftrt (match_operand:DI 2 "const_int_operand" "")
+ (subreg:SI (clz:DI (match_dup 1)) 4))))
+
+ (const_int 64))
+ (zero_extend:TI (clz:DI (match_dup 1)))))
+ (clobber (reg:CC CC_REGNUM))]
+ "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
+ == (unsigned HOST_WIDE_INT) 1 << 63
+ && TARGET_EXTIMM && TARGET_64BIT"
+ "flogr\t%0,%1"
+ [(set_attr "op_type" "RRE")])
+
+
+;;
;;- Rotate instructions.
;;