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[PATCH] S/390: backend fixes for -mzarch used with -m31
- From: Andreas Krebbel <krebbel1 at de dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Fri, 12 Aug 2005 12:28:36 +0200
- Subject: [PATCH] S/390: backend fixes for -mzarch used with -m31
Hi,
this is a collection of 5 small s390 back end fixes/enhancements:
(1) s390_single_part and s390_extract_part fail when they are
used to extract 32 bit integer parts because a missing type
cast when the bitmask is calculated.
(2) The N constraint can't deal with SImode parts.
(3) In s390_output_mi_thunk we have used a 64bit loads even on 31bit systems.
(4) movdi_31 and movdf_31 are lacking the long displacement versions of load
and store multiple what causes "unrecognizable insn" failures if the flags
-m31 and -mzarch are used in conjunction.
(5) The llgt instructions are available on zArchitecture machines regardless
whether 31bit or 64bit binaries are created. The patch enables the respective
insn pattern and the splitter.
Bootstrapped and testsuite run (4.0 and 4.1)
without regressions on s390 and s390x.
OK for mainline and 4.0?
Bye,
-Andreas-
2005-08-11 Andreas Krebbel <krebbel1@de.ibm.com>
* config/s390/s390.c (s390_extract_part, s390_single_part):
Type cast added.
(s390_const_ok_for_constraint_p): Added SImode to the N constraint.
(s390_output_mi_thunk): Don't use lg on 31 bit.
* config/s390/s390.md ("*movdi_31", "*movdf_31"): Added lmy and stmy.
("*llgt_sisi" and splitter): Replaced TARGET_64BIT with TARGET_ZARCH.
Index: gcc/config/s390/s390.c
===================================================================
--- gcc/config/s390/s390.c.orig 2005-08-11 12:38:21.000000000 +0200
+++ gcc/config/s390/s390.c 2005-08-11 13:29:11.000000000 +0200
@@ -941,7 +941,8 @@ s390_extract_part (rtx op, enum machine_
unsigned HOST_WIDE_INT value = 0;
int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
int part_bits = GET_MODE_BITSIZE (mode);
- unsigned HOST_WIDE_INT part_mask = (1 << part_bits) - 1;
+ unsigned HOST_WIDE_INT part_mask
+ = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
int i;
for (i = 0; i < max_parts; i++)
@@ -970,7 +971,8 @@ s390_single_part (rtx op,
{
unsigned HOST_WIDE_INT value = 0;
int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
- unsigned HOST_WIDE_INT part_mask = (1 << GET_MODE_BITSIZE (part_mode)) - 1;
+ unsigned HOST_WIDE_INT part_mask
+ = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
int i, part = -1;
if (GET_CODE (op) != CONST_INT)
@@ -1829,8 +1831,9 @@ s390_const_ok_for_constraint_p (HOST_WID
switch (str[2])
{
- case 'H': part_mode = HImode; break;
- case 'Q': part_mode = QImode; break;
+ case 'Q': part_mode = QImode; break;
+ case 'H': part_mode = HImode; break;
+ case 'S': part_mode = SImode; break;
default: return 0;
}
@@ -7785,12 +7788,12 @@ s390_output_mi_thunk (FILE *file, tree t
{
if (CONST_OK_FOR_CONSTRAINT_P (vcall_offset, 'J', "J"))
{
- output_asm_insn ("lg\t%4,0(%1)", op);
+ output_asm_insn ("l\t%4,0(%1)", op);
output_asm_insn ("a\t%1,%3(%4)", op);
}
else if (DISP_IN_RANGE (vcall_offset))
{
- output_asm_insn ("lg\t%4,0(%1)", op);
+ output_asm_insn ("l\t%4,0(%1)", op);
output_asm_insn ("ay\t%1,%3(%4)", op);
}
else if (CONST_OK_FOR_CONSTRAINT_P (vcall_offset, 'K', "K"))
Index: gcc/config/s390/s390.md
===================================================================
--- gcc/config/s390/s390.md.orig 2005-08-11 12:38:21.000000000 +0200
+++ gcc/config/s390/s390.md 2005-08-11 12:38:21.000000000 +0200
@@ -933,12 +933,14 @@
s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
(define_insn "*movdi_31"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q")
- (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q")
+ (match_operand:DI 1 "general_operand" "Q,S,d,d,dKm,d,*f,R,T,*f,*f,Q"))]
"!TARGET_64BIT"
"@
lm\t%0,%N0,%S1
+ lmy\t%0,%N0,%S1
stm\t%1,%N1,%S0
+ stmy\t%1,%N1,%S0
#
#
ldr\t%0,%1
@@ -947,8 +949,8 @@
std\t%1,%0
stdy\t%1,%0
#"
- [(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS")
- (set_attr "type" "lm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
+ [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS")
+ (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
@@ -1393,8 +1395,8 @@
(set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
(define_insn "*movdf_31"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,Q,d,o,Q")
- (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,d,dKm,d,Q"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,Q,S,d,o,Q")
+ (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))]
"!TARGET_64BIT"
"@
lzdr\t%0
@@ -1404,12 +1406,15 @@
std\t%1,%0
stdy\t%1,%0
lm\t%0,%N0,%S1
+ lmy\t%0,%N0,%S1
stm\t%1,%N1,%S0
+ stmy\t%1,%N1,%S0
#
#
#"
- [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RS,*,*,SS")
- (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lm,stm,*,*,*")])
+ [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS")
+ (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,\
+ lm,lm,stm,stm,*,*,*")])
(define_split
[(set (match_operand:DF 0 "nonimmediate_operand" "")
@@ -2604,7 +2609,7 @@
[(set (match_operand:SI 0 "register_operand" "=d,d")
(and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
(const_int 2147483647)))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
llgtr\t%0,%1
llgt\t%0,%1"
@@ -2625,7 +2630,7 @@
(and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
(const_int 2147483647)))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT && reload_completed"
+ "TARGET_ZARCH && reload_completed"
[(set (match_dup 0)
(and:GPR (match_dup 1)
(const_int 2147483647)))]