[patch] fix rs6000-power2-2.c

[Eric Christopher <echristo at apple dot com>]

This patch fixes the testcase rs6000-power2-2.c which tests for  
generation of the TFmode move instructions. We were failing the  
testcase because while we would generate the instruction in peephole2  
we would recognize the splitter version of the pattern and split just  
before code generation.

Tested on ppc-darwin8, though this isn't as helpful since it isn't a  
power2 architecture machine. No regressions, fixes the aforementioned  
testcases. OK?

2005-08-08  Eric Christopher  <echristo@apple.com>

        * config/rs6000/rs6000.md (*movtf_internal): Disable pattern
        for power2.

Also while I was at it I rewrote mems_ok_for_quad_peep since it  
seemed a bit confusingly written. This code looks a bit cleaner, and  
still passes all of the tests. Tested the same way. OK?

2005-08-08  Eric Christopher  <echristo@apple.com>

       * config/rs6000/rs6000.c (mems_ok_for_quad_peep): Rewrite.


-eric

Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.392
diff -u -p -w -r1.392 rs6000.md
--- rs6000.md   15 Jul 2005 01:44:34 -0000      1.392
+++ rs6000.md   8 Aug 2005 23:16:29 -0000
@@ -7844,11 +7844,19 @@
; It's important to list the o->f and f->o moves before f->f because
; otherwise reload, given m->f, will try to pick f->f and reload it,
; which doesn't make progress.  Likewise r->Y must be before r->r.
+; Do not recognize this under TARGET_POWER2 since we have other  
instructions to
+; match this and do not want to split.
(define_insn_and_split "*movtf_internal"
   [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
        (match_operand:TF 1 "input_operand"         "f,o,f,YGHF,r,r"))]
   "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
+   && !(TARGET_POWER2
+       && gpc_reg_operand (operands[0], TFmode)
+       && memory_operand (operands[1], TFmode))
+   && !(TARGET_POWER2
+       && memory_operand (operands[0], TFmode)
+       && gpc_reg_operand (operands[1], TFmode))
    && (gpc_reg_operand (operands[0], TFmode)
        || gpc_reg_operand (operands[1], TFmode))"
   "#"

Index: rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.858
diff -u -p -w -r1.858 rs6000.c
--- rs6000.c    8 Aug 2005 16:36:19 -0000       1.858
+++ rs6000.c    8 Aug 2005 23:27:08 -0000
@@ -9647,8 +9647,8 @@ int
mems_ok_for_quad_peep (rtx mem1, rtx mem2)
{
   rtx addr1, addr2;
-  unsigned int reg1;
-  int offset1;
+  unsigned int reg1, reg2;
+  int offset1, offset2;
   /* The mems cannot be volatile.  */
   if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
@@ -9681,23 +9681,36 @@ mems_ok_for_quad_peep (rtx mem1, rtx mem
       offset1 = 0;
     }
-  /* Make sure the second address is a (mem (plus (reg) (const_int)))
-     or if it is (mem (reg)) then make sure that offset1 is -8 and  
the same
-     register as addr1.  */
-  if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO  
(addr2))
-    return 1;
-  if (GET_CODE (addr2) != PLUS)
+  /* And now for the second addr.  */
+  if (GET_CODE (addr2) == PLUS)
+    {
+      /* If not a REG, return zero.  */
+      if (GET_CODE (XEXP (addr2, 0)) != REG)
     return 0;
-
-  if (GET_CODE (XEXP (addr2, 0)) != REG
-      || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
+      else
+       {
+         reg2 = REGNO (XEXP (addr2, 0));
+         /* The offset must be constant. */
+         if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
     return 0;

   /* All the tests passed.  addr1 and addr2 are valid for lfq or stfq