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[Patch] MIPS: Add cost for 5KC/5KF and dfa pipeline.
- From: David Ung <davidu at mips dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Fri, 29 Jul 2005 15:21:49 +0100
- Subject: [Patch] MIPS: Add cost for 5KC/5KF and dfa pipeline.
- References: <1118759617.1641.806.camel@localhost.localdomain> <1118774435.3242.25.camel@dzur.sfbay.redhat.com> <1118841695.1602.40.camel@localhost.localdomain>
hi, this patch adds the costs for the 5kc and 5kf processors. The DFA
pipeline description is included.
regressions ok, tested on mipsisa64, mips-sim-idt64/-march=5kf
David.
* config/mips/mips.c (mips_cpu_info_table): Add 5kf to the table.
(mips_rtx_cost_data): Add costs for 5kc and 5kf.
* config/mips/mips.h (processor_type): Add PROCESSOR_5KF.
* config/mips/mips.md (cpu): Add 5kf name.
(includes): Includes 5k.md.
* config/mips/5k.md: New DFA pipeline for the 5kc/5kf.
Index: gcc/config/mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.517
diff -c -p -b -r1.517 mips.c
*** gcc/config/mips/mips.c 23 Jul 2005 08:36:52 -0000 1.517
--- gcc/config/mips/mips.c 29 Jul 2005 14:19:11 -0000
*************** const struct mips_cpu_info mips_cpu_info
*** 748,753 ****
--- 748,754 ----
/* MIPS64 */
{ "5kc", PROCESSOR_5KC, 64 },
+ { "5kf", PROCESSOR_5KF, 64 },
{ "20kc", PROCESSOR_20KC, 64 },
{ "sb1", PROCESSOR_SB1, 64 },
{ "sr71000", PROCESSOR_SR71000, 64 },
*************** static struct mips_rtx_cost_data const m
*** 813,819 ****
4 /* memory_latency */
},
{ /* 5KC */
! DEFAULT_COSTS
},
{ /* 20KC */
DEFAULT_COSTS
--- 814,839 ----
4 /* memory_latency */
},
{ /* 5KC */
! SOFT_FP_COSTS,
! COSTS_N_INSNS (4), /* int_mult_si */
! COSTS_N_INSNS (11), /* int_mult_di */
! COSTS_N_INSNS (36), /* int_div_si */
! COSTS_N_INSNS (68), /* int_div_di */
! 1, /* branch_cost */
! 4 /* memory_latency */
! },
! { /* 5KF */
! COSTS_N_INSNS (4), /* fp_add */
! COSTS_N_INSNS (4), /* fp_mult_sf */
! COSTS_N_INSNS (5), /* fp_mult_df */
! COSTS_N_INSNS (17), /* fp_div_sf */
! COSTS_N_INSNS (32), /* fp_div_df */
! COSTS_N_INSNS (4), /* int_mult_si */
! COSTS_N_INSNS (11), /* int_mult_di */
! COSTS_N_INSNS (36), /* int_div_si */
! COSTS_N_INSNS (68), /* int_div_di */
! 1, /* branch_cost */
! 4 /* memory_latency */
},
{ /* 20KC */
DEFAULT_COSTS
Index: gcc/config/mips/mips.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.h,v
retrieving revision 1.400
diff -c -p -b -r1.400 mips.h
*** gcc/config/mips/mips.h 23 Jul 2005 08:36:53 -0000 1.400
--- gcc/config/mips/mips.h 29 Jul 2005 14:19:31 -0000
*************** enum processor_type {
*** 36,41 ****
--- 36,42 ----
PROCESSOR_4KC,
PROCESSOR_4KP,
PROCESSOR_5KC,
+ PROCESSOR_5KF,
PROCESSOR_20KC,
PROCESSOR_24K,
PROCESSOR_24KX,
Index: gcc/config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.327
diff -c -p -b -r1.327 mips.md
*** gcc/config/mips/mips.md 23 Jul 2005 08:36:54 -0000 1.327
--- gcc/config/mips/mips.md 29 Jul 2005 14:19:50 -0000
***************
*** 336,342 ****
;; Attribute describing the processor. This attribute must match exactly
;; with the processor_type enumeration in mips.h.
(define_attr "cpu"
! "r3000,4kc,4kp,5kc,20kc,24k,24kx,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
(const (symbol_ref "mips_tune")))
;; The type of hardware hazard associated with this instruction.
--- 336,342 ----
;; Attribute describing the processor. This attribute must match exactly
;; with the processor_type enumeration in mips.h.
(define_attr "cpu"
! "r3000,4kc,4kp,5kc,5kf,20kc,24k,24kx,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
(const (symbol_ref "mips_tune")))
;; The type of hardware hazard associated with this instruction.
***************
*** 571,576 ****
--- 571,577 ----
(define_cpu_unit "imuldiv" "imuldiv")
(include "4k.md")
+ (include "5k.md")
(include "24k.md")
(include "3000.md")
(include "4000.md")
Index: gcc/config/mips/5k.md
===================================================================
;; DFA-based pipeline descriptions for MIPS32 5K processor family
;; Contributed by David Ung (davidu@mips.com)
;; and Nigel Stephens (nigel@mips.com)
;;
;; References:
;; "MIPS64 5K Processor Core Family Software User's Manual,
;; Doc no: MD00012, Rev 2.09, Jan 28, 2005."
;;
;; 5Kc - Single issue with no floating point unit.
;; 5kf - Separate floating point pipe which can dual-issue with the
;; integer pipe.
;;
;; Copyright (C) 2005 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 2, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING. If not, write to the
;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
;; MA 02110-1301, USA.
(define_automaton "r5k_cpu, r5k_mdu, r5k_fpu")
;; Integer execution unit.
(define_cpu_unit "r5k_ixu_arith" "r5k_cpu")
(define_cpu_unit "r5k_ixu_mpydiv" "r5k_mdu")
(define_cpu_unit "r5kf_fpu_arith" "r5k_fpu")
(define_insn_reservation "r5k_int_load" 2
(and (eq_attr "cpu" "5kc,5kf")
(eq_attr "type" "load"))
"r5k_ixu_arith")
(define_insn_reservation "r5k_int_prefetch" 1
(and (eq_attr "cpu" "5kc,5kf")
(eq_attr "type" "prefetch,prefetchx"))
"r5k_ixu_arith")
(define_insn_reservation "r5k_int_store" 1
(and (eq_attr "cpu" "5kc,5kf")
(eq_attr "type" "store"))
"r5k_ixu_arith")
;; Divides
(define_insn_reservation "r5k_int_divsi" 34
(and (eq_attr "cpu" "5kc,5kf")
(and (eq_attr "type" "idiv")
(eq_attr "mode" "!DI")))
"r5k_ixu_arith+(r5k_ixu_mpydiv*34)")
(define_insn_reservation "r5k_int_divdi" 66
(and (eq_attr "cpu" "5kc,5kf")
(and (eq_attr "type" "idiv")
(eq_attr "mode" "DI")))
"r5k_ixu_arith+(r5k_ixu_mpydiv*66)")
;; 32x32 multiply
;; 32x16 is faster, but there's no way to detect this
(define_insn_reservation "r5k_int_mult" 2
(and (eq_attr "cpu" "5kc,5kf")
(and (eq_attr "type" "imul,imadd")
(eq_attr "mode" "SI")))
"r5k_ixu_arith+(r5k_ixu_mpydiv*2)")
;; 64x64 multiply
(define_insn_reservation "r5k_int_mult_64" 9
(and (eq_attr "cpu" "5kc,5kf")
(and (eq_attr "type" "imul,imadd")
(eq_attr "mode" "DI")))
"r5k_ixu_arith+(r5k_ixu_mpydiv*2)")
;; 3 operand MUL 32x32
(define_insn_reservation "r5k_int_mul" 4
(and (eq_attr "cpu" "5kc,5kf")
(and (eq_attr "type" "imul3")
(eq_attr "mode" "SI")))
"r5k_ixu_arith+(r5k_ixu_mpydiv*2)")
;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency.
(define_insn_reservation "r5k_int_mthilo" 1
(and (eq_attr "cpu" "5kc,5kf")
(eq_attr "type" "mthilo"))
"r5k_ixu_arith+r5k_ixu_mpydiv")
;; Move from HI/LO -> integer operation has a 2 cycle latency.
(define_insn_reservation "r5k_int_mfhilo" 2
(and (eq_attr "cpu" "5kc,5kf")
(eq_attr "type" "mfhilo"))
"r5k_ixu_arith+r5k_ixu_mpydiv")
;; All other integer insns.
(define_insn_reservation "r5k_int_alu" 1
(and (eq_attr "cpu" "5kc,5kf")
(eq_attr "type" "arith,condmove,shift,const,nop,slt"))
"r5k_ixu_arith")
(define_insn_reservation "r5k_int_branch" 1
(and (eq_attr "cpu" "5kc,5kf")
(eq_attr "type" "branch"))
"r5k_ixu_arith")
;; JR/JALR always cause one pipeline bubble because of interlock.
(define_insn_reservation "r5k_int_jump" 2
(and (eq_attr "cpu" "5kc,5kf")
(eq_attr "type" "jump,call"))
"r5k_ixu_arith")
;; Any -> JR/JALR (without dependency) : 1 clock issue delay
;; Any -> JR/JALR (with dependency) : 2 clock issue delay
;; load -> JR/JALR (with dependency) : 3 clock issue delay
;; mfhilo -> JR/JALR (with dependency) : 3 clock issue delay
;; mul -> JR/JALR (with dependency) : 3 clock issue delay
(define_bypass 2 "r5k_int_alu" "r5k_int_jump")
(define_bypass 3 "r5k_int_load" "r5k_int_jump")
(define_bypass 3 "r5k_int_mfhilo" "r5k_int_jump")
(define_bypass 3 "r5k_int_mul" "r5k_int_jump")
;; Unknown or multi - single issue
(define_insn_reservation "r5k_int_unknown" 1
(and (eq_attr "cpu" "5kc,5kf")
(eq_attr "type" "unknown,multi"))
"r5k_ixu_arith+r5k_ixu_mpydiv")
;; Floating Point Instructions
;; The 5Kf is a partial dual-issue cpu which can dual issue an integer
;; and floating-point instruction in the same cycle.
;; fadd, fabs, fneg
(define_insn_reservation "r5kf_fadd" 4
(and (eq_attr "cpu" "5kf")
(eq_attr "type" "fadd,fabs,fneg"))
"r5kf_fpu_arith")
;; fmove, fcmove
(define_insn_reservation "r5kf_fmove" 4
(and (eq_attr "cpu" "5kf")
(eq_attr "type" "fmove"))
"r5kf_fpu_arith")
;; fload
(define_insn_reservation "r5kf_fload" 3
(and (eq_attr "cpu" "5kf")
(eq_attr "type" "fpload,fpidxload"))
"r5kf_fpu_arith")
;; fstore
(define_insn_reservation "r5kf_fstore" 1
(and (eq_attr "cpu" "5kf")
(eq_attr "type" "fpstore"))
"r5kf_fpu_arith")
;; fmul, fmadd
(define_insn_reservation "r5kf_fmul_sf" 4
(and (eq_attr "cpu" "5kf")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "SF")))
"r5kf_fpu_arith")
(define_insn_reservation "r5kf_fmul_df" 5
(and (eq_attr "cpu" "5kf")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "DF")))
"r5kf_fpu_arith*2")
;; fdiv, fsqrt, frsqrt
(define_insn_reservation "r5kf_fdiv_sf" 17
(and (eq_attr "cpu" "5kf")
(and (eq_attr "type" "fdiv,fsqrt,frsqrt")
(eq_attr "mode" "SF")))
"r5kf_fpu_arith*14")
(define_insn_reservation "r5kf_fdiv_df" 32
(and (eq_attr "cpu" "5kf")
(and (eq_attr "type" "fdiv,fsqrt")
(eq_attr "mode" "DF")))
"r5kf_fpu_arith*29")
;; frsqrt
(define_insn_reservation "r5kf_frsqrt_df" 35
(and (eq_attr "cpu" "5kf")
(and (eq_attr "type" "frsqrt")
(eq_attr "mode" "DF")))
"r5kf_fpu_arith*31")
;; fcmp
(define_insn_reservation "r5kf_fcmp" 2
(and (eq_attr "cpu" "5kf")
(eq_attr "type" "fcmp"))
"r5kf_fpu_arith")
;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on condition)
(define_bypass 1 "r5kf_fcmp" "r5kf_fmove")
;; fcvt (cvt.d.s, cvt.[sd].[wl]
(define_insn_reservation "r5kf_fcvt_d2s" 4
(and (eq_attr "cpu" "5kf")
(and (eq_attr "type" "fcvt")
(eq_attr "cnv_mode" "I2S,I2D,S2D")))
"r5kf_fpu_arith")
;; fcvt (cvt.s.d)
(define_insn_reservation "r5kf_fcvt_s2d" 6
(and (eq_attr "cpu" "5kc")
(and (eq_attr "type" "fcvt")
(eq_attr "cnv_mode" "D2S")))
"r5kf_fpu_arith")
;; fcvt (cvt.[wl].[sd], etc)
(define_insn_reservation "r5kf_fcvt_f2i" 5
(and (eq_attr "cpu" "5kf")
(and (eq_attr "type" "fcvt")
(eq_attr "cnv_mode" "S2I,D2I")))
"r5kf_fpu_arith")
;; fxfer (mfc1, mfhc1, mtc1, mthc1) - single issue
(define_insn_reservation "r5kf_fxfer" 2
(and (eq_attr "cpu" "5kf")
(eq_attr "type" "xfer"))
"r5k_ixu_arith+r5kf_fpu_arith")