This is the mail archive of the
mailing list for the GCC project.
Re: PATCH RFA: Use clz for MIPS ffs
On Wed, Jul 13, 2005 at 07:58:32AM +0100, Richard Sandiford wrote:
> OK, I know this going to be annoying, but there's nothing really
> MIPS-specific about this expansion either, is there? It's remarkably
> similar to the ARM version, for instance.
I certainly wouldn't stand in the way of this. There's another
copy in the rs6000 back end.
The initial reason this wasn't done generically was that clz is
not always defined for zero (thanks Intel). We added
CLZ_DEFINED_VALUE_AT_ZERO later. And with that we could generate
reasonable code for ffs generically. In particular, we can see
that we don't need an extra conditional if clz(0) == bitsize.
And here's where you have to start asking questions about how much
to do generically.
The Alpha port expands ffs as
t1 = ctz(in);
t2 = t1 + 1;
out = (in == 0 ? 0 : t2);
Note the ctz instead of clz. We need two fixup insns to match ffs
semantics, marginally better than the 3 fixup insns that would are
needed for the clz expansion. But it would appear that alpha is
one of the few targets to implement both clz and ctz in hw.
The ia64 port expands ffs as
t1 = in - 1;
t2 = in ^ t1;
t3 = popcount(t2);
out = (in == 0 ? 0 : t3);
which is kinda cool, since it doesn't have either clz or ctz
natively. In theory sparc64 would want the same implementation,
but Sun never got around to actually implementing the popc insn
that they reserved in the isa. And since Sun has killed Sparc
in favour of amd64 it seems unlikely that it'll ever matter.
So. How much work does someone feel like doing?
PS: The "ctz" pattern has the same kinds of duplication in the arm
and rs6000 backends that mips would want to add.