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PATCH RFA: Use clz for MIPS ffs


Paul Koning <pkoning@equallogic.com> writes:

> Ideally, the ffs pattern should take advantage of CLZ, if it exists on
> the target.  Then it clearly would be a win for -O2 and possibly even
> for -Os.

Here is the patch for that.  I tested this on the MIPS simulator with
and without -mips32.  With -mips32 it generates inline code, without
-mips32 it does not.

OK for mainline?

Ian


2005-07-12  Ian Lance Taylor  <ian@airs.com>

	* config/mips/mips.md (ffs<mode>2): New define_expand.


Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.326
diff -p -u -r1.326 mips.md
--- config/mips/mips.md	11 Jul 2005 18:48:37 -0000	1.326
+++ config/mips/mips.md	13 Jul 2005 01:36:19 -0000
@@ -1906,6 +1906,32 @@
    (set_attr "mode" "<UNITMODE>")])
 
 ;;
+;;  ....................
+;;
+;;	FIND FIRST BIT INSTRUCTION
+;;
+;;  ....................
+;;
+
+(define_expand "ffs<mode>2"
+  [(set (match_operand:GPR 0 "register_operand" "")
+	(ffs:GPR (match_operand:GPR 1 "register_operand" "")))]
+  "ISA_HAS_CLZ_CLO"
+{
+  rtx r1, r2, r3, r4;
+
+  r1 = gen_reg_rtx (<MODE>mode);
+  r2 = gen_reg_rtx (<MODE>mode);
+  r3 = gen_reg_rtx (<MODE>mode);
+  r4 = gen_reg_rtx (<MODE>mode);
+  emit_insn (gen_neg<mode>2 (r1, operands[1]));
+  emit_insn (gen_and<mode>3 (r2, operands[1], r1));
+  emit_insn (gen_clz<mode>2 (r3, r2));
+  emit_move_insn (r4, GEN_INT (GET_MODE_BITSIZE (<MODE>mode)));
+  emit_insn (gen_sub<mode>3 (operands[0], r4, r3));
+  DONE;
+})
+;;
 ;;  ...................
 ;;
 ;;  Count leading zeroes.


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