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Re: [PATCH] Complex MEM adjust_address instead of subreg (PR middle-end/21742)
Appended is the revised patch. The comments have been updated to
try to capture the insight and explanation from this email discussion.
Also, adjust_address() was changed to adjust_address_nv().
Okay for mainline after a successful bootstrap and regression
test?
Thanks, David
PR middle-end/21742
* expr.c (write_complex_part): Use adjust_address for MEM.
(read_complex_part): Same.
Index: expr.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/expr.c,v
retrieving revision 1.798
diff -c -p -r1.798 expr.c
*** expr.c 25 Jun 2005 01:59:50 -0000 1.798
--- expr.c 29 Jun 2005 23:50:41 -0000
*************** write_complex_part (rtx cplx, rtx val, b
*** 2656,2661 ****
--- 2656,2670 ----
imode = GET_MODE_INNER (cmode);
ibitsize = GET_MODE_BITSIZE (imode);
+ /* For MEMs simplify_gen_subreg may generate an invalid new address
+ because, e.g., the original address is considered mode-dependent
+ by the target, which restricts simplify_subreg from invoking
+ adjust_address_nv. Instead of preparing fallback support for an
+ invalid address, we call adjust_address_nv directly. */
+ if (MEM_P (cplx))
+ emit_move_insn (adjust_address_nv (cplx, imode, imag_p ? ibitsize : 0),
+ val);
+
/* If the sub-object is at least word sized, then we know that subregging
will work. This special case is important, since store_bit_field
wants to operate on integer modes, and there's rarely an OImode to
*************** write_complex_part (rtx cplx, rtx val, b
*** 2667,2677 ****
where the natural size of floating-point regs is 32-bit. */
|| (REG_P (cplx)
&& REGNO (cplx) < FIRST_PSEUDO_REGISTER
! && hard_regno_nregs[REGNO (cplx)][cmode] % 2 == 0)
! /* For MEMs we always try to make a "subreg", that is to adjust
! the MEM, because store_bit_field may generate overly
! convoluted RTL for sub-word fields. */
! || MEM_P (cplx))
{
rtx part = simplify_gen_subreg (imode, cplx, cmode,
imag_p ? GET_MODE_SIZE (imode) : 0);
--- 2676,2682 ----
where the natural size of floating-point regs is 32-bit. */
|| (REG_P (cplx)
&& REGNO (cplx) < FIRST_PSEUDO_REGISTER
! && hard_regno_nregs[REGNO (cplx)][cmode] % 2 == 0))
{
rtx part = simplify_gen_subreg (imode, cplx, cmode,
imag_p ? GET_MODE_SIZE (imode) : 0);
*************** read_complex_part (rtx cplx, bool imag_p
*** 2716,2721 ****
--- 2721,2734 ----
}
}
+ /* For MEMs simplify_gen_subreg may generate an invalid new address
+ because, e.g., the original address is considered mode-dependent
+ by the target, which restricts simplify_subreg from invoking
+ adjust_address_nv. Instead of preparing fallback support for an
+ invalid address, we call adjust_address_nv directly. */
+ if (MEM_P (cplx))
+ return adjust_address_nv (cplx, imode, imag_p ? ibitsize : 0);
+
/* If the sub-object is at least word sized, then we know that subregging
will work. This special case is important, since extract_bit_field
wants to operate on integer modes, and there's rarely an OImode to
*************** read_complex_part (rtx cplx, bool imag_p
*** 2727,2737 ****
where the natural size of floating-point regs is 32-bit. */
|| (REG_P (cplx)
&& REGNO (cplx) < FIRST_PSEUDO_REGISTER
! && hard_regno_nregs[REGNO (cplx)][cmode] % 2 == 0)
! /* For MEMs we always try to make a "subreg", that is to adjust
! the MEM, because extract_bit_field may generate overly
! convoluted RTL for sub-word fields. */
! || MEM_P (cplx))
{
rtx ret = simplify_gen_subreg (imode, cplx, cmode,
imag_p ? GET_MODE_SIZE (imode) : 0);
--- 2740,2746 ----
where the natural size of floating-point regs is 32-bit. */
|| (REG_P (cplx)
&& REGNO (cplx) < FIRST_PSEUDO_REGISTER
! && hard_regno_nregs[REGNO (cplx)][cmode] % 2 == 0))
{
rtx ret = simplify_gen_subreg (imode, cplx, cmode,
imag_p ? GET_MODE_SIZE (imode) : 0);