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Blackfin patch: DImode shifts by one
- From: Bernd Schmidt <bernds_cb1 at t-online dot de>
- To: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Sat, 25 Jun 2005 13:54:22 +0200
- Subject: Blackfin patch: DImode shifts by one
This implements a small optimization for DImode shifts where the shift
count is 1. We can do those as a pair of 33 bit rotates. This triggers
a few times in libgcc.
Bernd
* config/bfin/bfin.md (ror_one, rol_one, ashrdi3, ashldi3, lshrdi3):
New patterns.
(movbi): Add alternative to set CC to zero.
(compare_eq, compare_ne, compare_le, compare_lt, compare_leu,
compare_ltu): Now named patterns.
Index: config/bfin/bfin.md
===================================================================
RCS file: /cvsroot/gcc3/gcc-3.4/gcc/config/bfin/bfin.md,v
retrieving revision 1.73
diff -c -p -r1.73 bfin.md
*** config/bfin/bfin.md 8 Jun 2005 08:16:31 -0000 1.73
--- config/bfin/bfin.md 25 Jun 2005 09:49:11 -0000
***************
*** 336,343 ****
})
(define_insn "movbi"
! [(set (match_operand:BI 0 "nonimmediate_operand" "=x,x,d,mr,C,d")
! (match_operand:BI 1 "general_operand" "x,xKs3,mr,d,d,C"))]
""
"@
--- 336,343 ----
})
(define_insn "movbi"
! [(set (match_operand:BI 0 "nonimmediate_operand" "=x,x,d,mr,C,d,C")
! (match_operand:BI 1 "general_operand" "x,xKs3,mr,d,d,C,P0"))]
""
"@
***************
*** 346,354 ****
%0 = %1;
%0 = %1;
CC = %1;
! %0 = CC;"
! [(set_attr "type" "move,mvi,mcld,mcst,compare,compare")
! (set_attr "length" "2,2,*,*,2,2")])
(define_insn "movpdi"
[(set (match_operand:PDI 0 "nonimmediate_operand" "=e,<,e")
--- 346,355 ----
%0 = %1;
%0 = %1;
CC = %1;
! %0 = CC;
! R0 = R0 | R0; CC = AC0;"
! [(set_attr "type" "move,mvi,mcld,mcst,compare,compare,alu0")
! (set_attr "length" "2,2,*,*,2,2,4")])
(define_insn "movpdi"
[(set (match_operand:PDI 0 "nonimmediate_operand" "=e,<,e")
***************
*** 1186,1191 ****
--- 1187,1278 ----
"%0 >>>= %2;"
[(set_attr "type" "shft")])
+ (define_insn "ror_one"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") (const_int 1))
+ (ashift:SI (zero_extend:SI (reg:BI REG_CC)) (const_int 31))))
+ (set (reg:BI REG_CC)
+ (zero_extract:BI (match_dup 1) (const_int 1) (const_int 0)))]
+ ""
+ "%0 = ROT %1 BY -1;"
+ [(set_attr "type" "shft")
+ (set_attr "length" "4")])
+
+ (define_insn "rol_one"
+ [(set (match_operand:SI 0 "register_operand" "+d")
+ (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") (const_int 1))
+ (zero_extend:SI (reg:BI REG_CC))))
+ (set (reg:BI REG_CC)
+ (zero_extract:BI (match_dup 1) (const_int 31) (const_int 0)))]
+ ""
+ "%0 = ROT %1 BY 1;"
+ [(set_attr "type" "shft")
+ (set_attr "length" "4")])
+
+ (define_expand "lshrdi3"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "general_operand" "")))]
+ ""
+ {
+ rtx lo_half[2], hi_half[2];
+
+ if (operands[2] != const1_rtx)
+ FAIL;
+ if (! rtx_equal_p (operands[0], operands[1]))
+ emit_move_insn (operands[0], operands[1]);
+
+ split_di (operands, 2, lo_half, hi_half);
+
+ emit_move_insn (bfin_cc_rtx, const0_rtx);
+ emit_insn (gen_ror_one (hi_half[0], hi_half[0]));
+ emit_insn (gen_ror_one (lo_half[0], lo_half[0]));
+ DONE;
+ })
+
+ (define_expand "ashrdi3"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "general_operand" "")))]
+ ""
+ {
+ rtx lo_half[2], hi_half[2];
+
+ if (operands[2] != const1_rtx)
+ FAIL;
+ if (! rtx_equal_p (operands[0], operands[1]))
+ emit_move_insn (operands[0], operands[1]);
+
+ split_di (operands, 2, lo_half, hi_half);
+
+ emit_insn (gen_compare_lt (gen_rtx_REG (BImode, REG_CC),
+ hi_half[1], const0_rtx));
+ emit_insn (gen_ror_one (hi_half[0], hi_half[0]));
+ emit_insn (gen_ror_one (lo_half[0], lo_half[0]));
+ DONE;
+ })
+
+ (define_expand "ashldi3"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (ashift:DI (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "general_operand" "")))]
+ ""
+ {
+ rtx lo_half[2], hi_half[2];
+
+ if (operands[2] != const1_rtx)
+ FAIL;
+ if (! rtx_equal_p (operands[0], operands[1]))
+ emit_move_insn (operands[0], operands[1]);
+
+ split_di (operands, 2, lo_half, hi_half);
+
+ emit_move_insn (bfin_cc_rtx, const0_rtx);
+ emit_insn (gen_rol_one (lo_half[0], lo_half[0]));
+ emit_insn (gen_rol_one (hi_half[0], hi_half[0]));
+ DONE;
+ })
+
(define_insn "lshrsi3"
[(set (match_operand:SI 0 "register_operand" "=d,a")
(lshiftrt:SI (match_operand:SI 1 "register_operand" " 0,a")
***************
*** 1420,1426 ****
DONE;
})
! (define_insn ""
[(set (match_operand:BI 0 "cc_operand" "=C,C")
(eq:BI (match_operand:SI 1 "register_operand" "d,a")
(match_operand:SI 2 "nonmemory_operand" "dKs3,aKs3")))]
--- 1507,1513 ----
DONE;
})
! (define_insn "compare_eq"
[(set (match_operand:BI 0 "cc_operand" "=C,C")
(eq:BI (match_operand:SI 1 "register_operand" "d,a")
(match_operand:SI 2 "nonmemory_operand" "dKs3,aKs3")))]
***************
*** 1428,1434 ****
"cc =%1==%2;"
[(set_attr "type" "compare")])
! (define_insn ""
[(set (match_operand:BI 0 "cc_operand" "=C,C")
(ne:BI (match_operand:SI 1 "register_operand" "d,a")
(match_operand:SI 2 "nonmemory_operand" "dKs3,aKs3")))]
--- 1515,1521 ----
"cc =%1==%2;"
[(set_attr "type" "compare")])
! (define_insn "compare_ne"
[(set (match_operand:BI 0 "cc_operand" "=C,C")
(ne:BI (match_operand:SI 1 "register_operand" "d,a")
(match_operand:SI 2 "nonmemory_operand" "dKs3,aKs3")))]
***************
*** 1436,1442 ****
"cc =%1!=%2;"
[(set_attr "type" "compare")])
! (define_insn ""
[(set (match_operand:BI 0 "cc_operand" "=C,C")
(lt:BI (match_operand:SI 1 "register_operand" "d,a")
(match_operand:SI 2 "nonmemory_operand" "dKs3,aKs3")))]
--- 1523,1529 ----
"cc =%1!=%2;"
[(set_attr "type" "compare")])
! (define_insn "compare_lt"
[(set (match_operand:BI 0 "cc_operand" "=C,C")
(lt:BI (match_operand:SI 1 "register_operand" "d,a")
(match_operand:SI 2 "nonmemory_operand" "dKs3,aKs3")))]
***************
*** 1444,1450 ****
"cc =%1<%2;"
[(set_attr "type" "compare")])
! (define_insn ""
[(set (match_operand:BI 0 "cc_operand" "=C,C")
(le:BI (match_operand:SI 1 "register_operand" "d,a")
(match_operand:SI 2 "nonmemory_operand" "dKs3,aKs3")))]
--- 1531,1537 ----
"cc =%1<%2;"
[(set_attr "type" "compare")])
! (define_insn "compare_le"
[(set (match_operand:BI 0 "cc_operand" "=C,C")
(le:BI (match_operand:SI 1 "register_operand" "d,a")
(match_operand:SI 2 "nonmemory_operand" "dKs3,aKs3")))]
***************
*** 1452,1458 ****
"cc =%1<=%2;"
[(set_attr "type" "compare")])
! (define_insn ""
[(set (match_operand:BI 0 "cc_operand" "=C,C")
(leu:BI (match_operand:SI 1 "register_operand" "d,a")
(match_operand:SI 2 "nonmemory_operand" "dKu3,aKu3")))]
--- 1539,1545 ----
"cc =%1<=%2;"
[(set_attr "type" "compare")])
! (define_insn "compare_leu"
[(set (match_operand:BI 0 "cc_operand" "=C,C")
(leu:BI (match_operand:SI 1 "register_operand" "d,a")
(match_operand:SI 2 "nonmemory_operand" "dKu3,aKu3")))]
***************
*** 1460,1466 ****
"cc =%1<=%2 (iu);"
[(set_attr "type" "compare")])
! (define_insn ""
[(set (match_operand:BI 0 "cc_operand" "=C,C")
(ltu:BI (match_operand:SI 1 "register_operand" "d,a")
(match_operand:SI 2 "nonmemory_operand" "dKu3,aKu3")))]
--- 1547,1553 ----
"cc =%1<=%2 (iu);"
[(set_attr "type" "compare")])
! (define_insn "compare_ltu"
[(set (match_operand:BI 0 "cc_operand" "=C,C")
(ltu:BI (match_operand:SI 1 "register_operand" "d,a")
(match_operand:SI 2 "nonmemory_operand" "dKu3,aKu3")))]