This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: [Patch] MIPS: mips16e machine patterns - zeb/zeh seb/seh
> > >
> > > This I don't get. Why not think of it this way (which I thought was
> > > what Richard was suggesting):
> > >
> > > A MIPS processor with MIPS16 support has two modes, 16-bit and 32-bit
> > > instructions.
> > >
> > > When you say -mips16 you get all of the instructions in the selected
> > > processor's 16-bit mode. If -march implies a processor which
> > > supports MIPS16e, then enable MIPS16e.
> >
> > To clear up any confusion, this was indeed what I was suggesting,
> > but I didn't word it as well.
> >
> > I just think that -mips16* flags should be _either_ a 16-bit mode
> > selector _or_ an ISA flag. David's third option is a bit of a hybrid.
> >
> > At the moment, -mips16 could be interpreted either way, because gcc
> > only knows about one 16-bit ISA.
>
> ok that puts us back to Richard's choice (b), I can live with that. :)
> So that means we abandant the -mips16e switch, and let the -march decide
> on what 16bit variant it wants to generate. Eg.
> -march=mip32 -mips16 => MIPS32 ISA and MIPS16e ASE.
> -march=mips3 -mips16 => MIPS3 ISA and MIPS16 ASE.
> So the GENERATE_MIPS16E macro will just be MIPS16 && mips_isa >= 32 for
> now.
> if later someone whats to add full MIPS16e to a non MIPS32/64 ISA, we'll
> extend the GENERATE_MIPS16E macro to include mips_arch == PROCESSOR_XXX.
> Is that ok with everyone?
following up from the above. If we are going to remove the -mips16e
option, we should probably make gas consisitent with gcc too. So what
becomes of ".set mips16e"? I guess one would just use the plan ".set
mips16" and let gas handle if the instructions are valid according to
the ISA or CPU type.
So here we have it then, the new patch.
2005-06-14 David Ung <davidu@mips.com>
* config/mips/mips.h (GENERATE_MIPS16E): New definition.
* config/mips/mips.md (zero_extend<SHORT:mode><GPR:mode>2):
Changed expand condition to exclude generating of "and" if
GENERATE_MIPS16E is true.
(*zero_extend<SHORT:mode><GPR:mode>2_mips16e): New pattern for
matching mips16e zeb/zeh.
(*extend<SHORT:mode><GPR:mode>2_mips16e): New pattern for matching
mips16e seb/seh.
(*extend<SHORT:mode><GPR:mode>2): Disable this pattern for
GENERATE_MIPS16E.
* doc/invoke.texi (MIPS Options): Add note that if -mips16 and ISA
is one of MIPS32/MIPS32R2/MIPS64, then the MIPS16e is used.
2005-06-14 David Ung <davidu@mips.com>
* gcc.target/mips/mips.exp (dg-mips-options): Include check of
-mips16e in isa.
* gcc.target/mips/mips16e-extends.c: New test for testing the
generation of MIPS16e zeb/zeh, seb/seh instructions.
Index: gcc/doc/invoke.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/invoke.texi,v
retrieving revision 1.632
diff -c -p -b -r1.632 invoke.texi
*** gcc/doc/invoke.texi 6 Jun 2005 02:32:27 -0000 1.632
--- gcc/doc/invoke.texi 14 Jun 2005 11:54:59 -0000
*************** Equivalent to @samp{-march=mips64}.
*** 9836,9842 ****
@itemx -mno-mips16
@opindex mips16
@opindex mno-mips16
! Use (do not use) the MIPS16 ISA@.
@item -mabi=32
@itemx -mabi=o64
--- 9836,9844 ----
@itemx -mno-mips16
@opindex mips16
@opindex mno-mips16
! Use (do not use) the MIPS16 ASE@.
!
! Note that if ISA is mips32/mips32r2/mips64, the MIPS16e ASE is used.
@item -mabi=32
@itemx -mabi=o64
Index: gcc/config/mips/mips.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.h,v
retrieving revision 1.396
diff -c -p -b -r1.396 mips.h
*** gcc/config/mips/mips.h 2 Jun 2005 18:08:19 -0000 1.396
--- gcc/config/mips/mips.h 14 Jun 2005 11:47:51 -0000
*************** extern const struct mips_rtx_cost_data *
*** 168,175 ****
We therefore disable GP-relative switch tables for n64 on IRIX targets. */
#define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
! /* Generate mips16 code */
#define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
/* Generic ISA defines. */
#define ISA_MIPS1 (mips_isa == 1)
--- 168,177 ----
We therefore disable GP-relative switch tables for n64 on IRIX targets. */
#define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
! /* Generate mips16 code */
#define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
+ /* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */
+ #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
/* Generic ISA defines. */
#define ISA_MIPS1 (mips_isa == 1)
Index: gcc/config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.322
diff -c -p -b -r1.322 mips.md
*** gcc/config/mips/mips.md 2 Jun 2005 18:08:20 -0000 1.322
--- gcc/config/mips/mips.md 14 Jun 2005 11:48:38 -0000
*************** beq\t%2,%.,1b\;\
*** 2319,2325 ****
(zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
""
{
! if (TARGET_MIPS16 && !memory_operand (operands[1], <SHORT:MODE>mode))
{
emit_insn (gen_and<GPR:mode>3 (operands[0],
gen_lowpart (<GPR:MODE>mode, operands[1]),
--- 2319,2326 ----
(zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
""
{
! if (TARGET_MIPS16 && !GENERATE_MIPS16E
! && !memory_operand (operands[1], <SHORT:MODE>mode))
{
emit_insn (gen_and<GPR:mode>3 (operands[0],
gen_lowpart (<GPR:MODE>mode, operands[1]),
*************** beq\t%2,%.,1b\;\
*** 2340,2345 ****
--- 2341,2354 ----
[(set_attr "type" "arith,load")
(set_attr "mode" "<GPR:MODE>")])
+ (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
+ "GENERATE_MIPS16E"
+ "ze<SHORT:size>\t%0"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "<GPR:MODE>")])
+
(define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
[(set (match_operand:GPR 0 "register_operand" "=d")
(zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
*************** beq\t%2,%.,1b\;\
*** 2418,2428 ****
(sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
"")
(define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
(sign_extend:GPR
(match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
! "!ISA_HAS_SEB_SEH"
"@
#
l<SHORT:size>\t%0,%1"
--- 2427,2447 ----
(sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
"")
+ (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
+ "GENERATE_MIPS16E"
+ "@
+ se<SHORT:size>\t%0
+ l<SHORT:size>\t%0,%1"
+ [(set_attr "type" "arith,load")
+ (set_attr "mode" "<GPR:MODE>")])
+
(define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
(sign_extend:GPR
(match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
! "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
"@
#
l<SHORT:size>\t%0,%1"
Index: gcc/testsuite/gcc.target/mips/mips.exp
===================================================================
RCS file: /cvs/gcc/gcc/gcc/testsuite/gcc.target/mips/mips.exp,v
retrieving revision 1.2
diff -c -p -b -r1.2 mips.exp
*** gcc/testsuite/gcc.target/mips/mips.exp 18 Apr 2005 20:34:36 -0000 1.2
--- gcc/testsuite/gcc.target/mips/mips.exp 14 Jun 2005 11:55:34 -0000
*************** proc dg-mips-options {args} {
*** 152,158 ****
if {$mips_mips16 || ($arch != $mips_arch && $mips_forced_isa)} {
set matches 0
}
! } elseif {[regexp -- {^-mips(.*)} $flag dummy isa] && $isa != 16} {
if {$mips_mips16 || ($isa != $mips_isa && $mips_forced_isa)} {
set matches 0
}
--- 152,159 ----
if {$mips_mips16 || ($arch != $mips_arch && $mips_forced_isa)} {
set matches 0
}
! } elseif {[regexp -- {^-mips(.*)} $flag dummy isa]
! && ![string match 16* $isa]} {
if {$mips_mips16 || ($isa != $mips_isa && $mips_forced_isa)} {
set matches 0
}
Index: gcc/testsuite/gcc.target/mips/mips16e-extends.c
===================================================================
/* { dg-do compile } */
/* { dg-mips-options "-Os -mips16e" } */
short cksum16 (unsigned long n)
{
unsigned long l;
l = validate (n, (n >> 16) + (n & 0xffff));
return l;
}
char cksum8 (unsigned long n)
{
unsigned long l;
l = validate (n, (n >> 8) + (n & 0xff));
return l;
}
/* { dg-final { scan-assembler "zeh" } } */
/* { dg-final { scan-assembler "seh" } } */
/* { dg-final { scan-assembler "zeb" } } */
/* { dg-final { scan-assembler "seb" } } */