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Re: [csl-sol210] Patch to disable ldd and std for 32-bit SPARC
On Fri, 20 May 2005, Eric Botcazou wrote:
> Some comments:
Thanks, I've applied the following patch to address those comments and to
fix a problem found in use of the patch (REG+REG addressing cannot be
allowed for DImode quantities with this option because such uses cannot be
split).
Regarding RTH's comments about the specification, the specification I was
given was to disable these instructions and this is apparently compatible
with Sun's compiler's default mode (presume 8-bit alignment but let buggy
programs not crash in this way); an approach which did reduce alignment
presumptions to 4 bytes everywhere (but without incompatibly changing the
ABI) would be reasonable but there are examples without long long which
are affected; one I was given is
struct {
int32_t x;
int32_t y;
double d;
};
where storing into x and y should not use std even though the structure
should be 8-byte-aligned.
--
Joseph S. Myers http://www.srcf.ucam.org/~jsm28/gcc/
jsm@polyomino.org.uk (personal mail)
joseph@codesourcery.com (CodeSourcery mail)
jsm28@gcc.gnu.org (Bugzilla assignments and CCs)
diff -rupN GCC.orig/ChangeLog.csl GCC/ChangeLog.csl
--- GCC.orig/ChangeLog.csl 2005-05-19 21:45:59.000000000 +0000
+++ GCC/ChangeLog.csl 2005-05-20 17:12:41.000000000 +0000
@@ -1,9 +1,19 @@
+2005-05-20 Joseph S. Myers <joseph@codesourcery.com>
+
+ * gcc/doc/invoke.texi: Correct typos in previous change.
+ * gcc/config/sparc/sparc.md (movdi_insn_sp32_v9_nolddstd,
+ movdi_insn_sp32_nolddstd): Give # alternatives length 2.
+ * gcc/config/sparc.c (save_regs, restore_regs,
+ sparc_flat_save_restore): Revert previous changes.
+ (legitimate_address_p): Do not allow REG+REG addressing for DImode
+ if !TARGET_INTEGER_LDD_STD.
+
2005-05-19 Joseph S. Myers <joseph@codesourcery.com>
* gcc/config/sparc/sparc.h (MASK_NO_INTEGER_LDD_STD,
TARGET_INTEGER_LDD_STD): New.
(TARGET_SWITCHES): Define -mno-integer-ldd-std option.
- * gcc/doc/invoke.texi (-mno-integer-std-ldd): Document.
+ * gcc/doc/invoke.texi (-mno-integer-ldd-std): Document.
* gcc/config/sparc/sparc.c (save_regs, restore_regs,
sparc_splitdi_legitimate, sparc_flat_save_restore): Check
TARGET_INTEGER_LDD_STD.
diff -rupN GCC.orig/gcc/config/sparc/sparc.c GCC/gcc/config/sparc/sparc.c
--- GCC.orig/gcc/config/sparc/sparc.c 2005-05-19 21:45:44.000000000 +0000
+++ GCC/gcc/config/sparc/sparc.c 2005-05-20 17:10:17.000000000 +0000
@@ -3400,6 +3400,9 @@ legitimate_address_p (enum machine_mode
if (TARGET_ARCH32 && !optimize
&& (mode == DFmode || mode == DImode))
return 0;
+ if (TARGET_ARCH32 && !TARGET_INTEGER_LDD_STD
+ && mode == DImode)
+ return 0;
}
else if (USE_AS_OFFSETABLE_LO10
&& GET_CODE (rs1) == LO_SUM
@@ -4140,8 +4143,7 @@ save_regs (FILE *file, int low, int high
{
if (regs_ever_live[i] && ! call_used_regs[i])
{
- if (TARGET_INTEGER_LDD_STD
- && regs_ever_live[i+1] && ! call_used_regs[i+1])
+ if (regs_ever_live[i+1] && ! call_used_regs[i+1])
{
fprintf (file, "\tstd\t%s, [%s+%d]\n",
reg_names[i], base, offset + 4 * n_regs);
@@ -4204,8 +4206,7 @@ restore_regs (FILE *file, int low, int h
for (i = low; i < high; i += 2)
{
if (regs_ever_live[i] && ! call_used_regs[i])
- if (TARGET_INTEGER_LDD_STD
- && regs_ever_live[i+1] && ! call_used_regs[i+1])
+ if (regs_ever_live[i+1] && ! call_used_regs[i+1])
fprintf (file, "\tldd\t[%s+%d], %s\n",
base, offset + 4 * n_regs, reg_names[i]),
n_regs += 2;
@@ -7766,8 +7767,7 @@ sparc_flat_save_restore (FILE *file, con
{
if ((gmask & (1L << regno)) != 0)
{
- if (TARGET_INTEGER_LDD_STD
- && (regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
+ if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
{
/* We can save two registers in a row. If we're not at a
double word boundary, move to one.
diff -rupN GCC.orig/gcc/config/sparc/sparc.md GCC/gcc/config/sparc/sparc.md
--- GCC.orig/gcc/config/sparc/sparc.md 2005-05-19 21:45:44.000000000 +0000
+++ GCC/gcc/config/sparc/sparc.md 2005-05-20 17:03:05.000000000 +0000
@@ -2150,7 +2150,7 @@
ldd\\t%1, %0
std\\t%1, %0"
[(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,fpmove,fpload,fpstore")
- (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,*,*,*")
+ (set_attr "length" "*,2,2,2,2,2,2,2,*,*,2,2,*,*,*")
(set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*")])
(define_insn "*movdi_insn_sp32"
@@ -2199,7 +2199,7 @@
#
#"
[(set_attr "type" "store,store,load,*,*,*,*,fpstore,fpload,*,*,*")
- (set_attr "length" "2,*,*,2,2,2,2,*,*,2,2,2")])
+ (set_attr "length" "2,2,2,2,2,2,2,*,*,2,2,2")])
;; The following are generated by sparc_emit_set_const64
(define_insn "*movdi_sp64_dbl"
diff -rupN GCC.orig/gcc/doc/invoke.texi GCC/gcc/doc/invoke.texi
--- GCC.orig/gcc/doc/invoke.texi 2005-05-19 21:45:44.000000000 +0000
+++ GCC/gcc/doc/invoke.texi 2005-05-20 17:01:42.000000000 +0000
@@ -368,7 +368,7 @@ in the following sections.
-mstack-bias -mno-stack-bias @gol
-munaligned-doubles -mno-unaligned-doubles @gol
-mv8plus -mno-v8plus -mvis -mno-vis @gol
--minteger-std-ldd -mno-integer-std-ldd @gol
+-minteger-ldd-std -mno-integer-ldd-std @gol
-mcypress -mf930 -mf934 @gol
-msparclite -msupersparc -mv8
-threads -pthreads}
@@ -6399,14 +6399,14 @@ mode for all SPARC-V9 processors.
With @option{-mvis}, GCC generates code that takes advantage of the UltraSPARC
Visual Instruction Set extensions. The default is @option{-mno-vis}.
-@item -minteger-std-ldd
-@itemx -mno-integer-std-ldd
-@opindex minteger-std-ldd
-@opindex mno-integer-std-ldd
-With @option{-mno-integer-std-ldd}, GCC does not use the @code{ldd}
+@item -minteger-ldd-std
+@itemx -mno-integer-ldd-std
+@opindex minteger-ldd-std
+@opindex mno-integer-ldd-std
+With @option{-mno-integer-ldd-std}, GCC does not use the @code{ldd}
and @code{std} instructions for integer operands in 32-bit mode. This
is for use with legacy code using 64-bit quantities which are not
-64-bit aligned. The default is @option{-minteger-std-ldd}.
+64-bit aligned. The default is @option{-minteger-ldd-std}.
@end table
These @samp{-m} options are supported in addition to the above