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RFC: MIPS clones without lwl/lwr/swl/swr


The patch below (for mainline) is an attempt to support MIPS clones
which don't have the patented lwl/lwr/swl/swr instructions.  This
would be useful mainly for the Realtek RTL8181 "Wireless LAN Access
Point / Gateway Controller", based on the Lexra core.  Linux/uClibc
port for the RTL8181 is available at http://rtl8181.sourceforge.net/ .

This is not tested (other than it compiles), so not meant for
inclusion in the official GCC source just yet - but I kindly ask
you (especially MIPS hackers, because I'm not yet very familiar
with this architecture) to review it and tell me if it looks good.

If -mpatfree is specified, use of lwl/lwr/swl/swr is disabled.
I understand that lack of these instructions will likely result in
less efficient code - that's OK, as long as the code is correct.
Suggestions for a better name for this option are also welcome.

Thanks,
Marek

Index: config/mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.502
diff -c -3 -p -r1.502 mips.c
*** config/mips/mips.c	9 May 2005 11:43:48 -0000	1.502
--- config/mips/mips.c	13 May 2005 14:23:42 -0000
*************** mips_block_move_straight (rtx dest, rtx 
*** 3079,3086 ****
       half-word alignment, it is usually better to move in half words.
       For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
       and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
!      Otherwise move word-sized chunks.  */
!   if (MEM_ALIGN (src) == BITS_PER_WORD / 2
        && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
      bits = BITS_PER_WORD / 2;
    else
--- 3079,3089 ----
       half-word alignment, it is usually better to move in half words.
       For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
       and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
!      Otherwise move word-sized chunks.  If lwl/lwr/swl/swr are not
!      available, move largest possible chunks allowed by alignment.  */
!   if (TARGET_PATFREE)
!     bits = MIN (MEM_ALIGN (src), MEM_ALIGN (dest));
!   else if (MEM_ALIGN (src) == BITS_PER_WORD / 2
        && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
      bits = BITS_PER_WORD / 2;
    else
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.317
diff -c -3 -p -r1.317 mips.md
*** config/mips/mips.md	9 May 2005 11:43:50 -0000	1.317
--- config/mips/mips.md	13 May 2005 14:23:44 -0000
*************** beq\t%2,%.,1b\;\
*** 2804,2810 ****
  	(sign_extract (match_operand:QI 1 "memory_operand")
  		      (match_operand 2 "immediate_operand")
  		      (match_operand 3 "immediate_operand")))]
!   "!TARGET_MIPS16"
  {
    if (mips_expand_unaligned_load (operands[0], operands[1],
  				  INTVAL (operands[2]),
--- 2804,2810 ----
  	(sign_extract (match_operand:QI 1 "memory_operand")
  		      (match_operand 2 "immediate_operand")
  		      (match_operand 3 "immediate_operand")))]
!   "!TARGET_MIPS16 && !TARGET_PATFREE"
  {
    if (mips_expand_unaligned_load (operands[0], operands[1],
  				  INTVAL (operands[2]),
*************** beq\t%2,%.,1b\;\
*** 2819,2825 ****
  	(zero_extract (match_operand:QI 1 "memory_operand")
  		      (match_operand 2 "immediate_operand")
  		      (match_operand 3 "immediate_operand")))]
!   "!TARGET_MIPS16"
  {
    if (mips_expand_unaligned_load (operands[0], operands[1],
  				  INTVAL (operands[2]),
--- 2819,2825 ----
  	(zero_extract (match_operand:QI 1 "memory_operand")
  		      (match_operand 2 "immediate_operand")
  		      (match_operand 3 "immediate_operand")))]
!   "!TARGET_MIPS16 && !TARGET_PATFREE"
  {
    if (mips_expand_unaligned_load (operands[0], operands[1],
  				  INTVAL (operands[2]),
*************** beq\t%2,%.,1b\;\
*** 2834,2840 ****
  		      (match_operand 1 "immediate_operand")
  		      (match_operand 2 "immediate_operand"))
  	(match_operand 3 "reg_or_0_operand"))]
!   "!TARGET_MIPS16"
  {
    if (mips_expand_unaligned_store (operands[0], operands[3],
  				   INTVAL (operands[1]),
--- 2834,2840 ----
  		      (match_operand 1 "immediate_operand")
  		      (match_operand 2 "immediate_operand"))
  	(match_operand 3 "reg_or_0_operand"))]
!   "!TARGET_MIPS16 && !TARGET_PATFREE"
  {
    if (mips_expand_unaligned_store (operands[0], operands[3],
  				   INTVAL (operands[1]),
*************** beq\t%2,%.,1b\;\
*** 2861,2867 ****
  	(unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
  		     (match_operand:QI 2 "memory_operand" "m")]
  		    UNSPEC_LOAD_LEFT))]
!   "!TARGET_MIPS16"
    "<load>l\t%0,%2"
    [(set_attr "type" "load")
     (set_attr "mode" "<MODE>")])
--- 2861,2867 ----
  	(unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
  		     (match_operand:QI 2 "memory_operand" "m")]
  		    UNSPEC_LOAD_LEFT))]
!   "!TARGET_MIPS16 && !TARGET_PATFREE"
    "<load>l\t%0,%2"
    [(set_attr "type" "load")
     (set_attr "mode" "<MODE>")])
*************** beq\t%2,%.,1b\;\
*** 2872,2878 ****
  		     (match_operand:QI 2 "memory_operand" "m")
  		     (match_operand:GPR 3 "register_operand" "0")]
  		    UNSPEC_LOAD_RIGHT))]
!   "!TARGET_MIPS16"
    "<load>r\t%0,%2"
    [(set_attr "type" "load")
     (set_attr "mode" "<MODE>")])
--- 2872,2878 ----
  		     (match_operand:QI 2 "memory_operand" "m")
  		     (match_operand:GPR 3 "register_operand" "0")]
  		    UNSPEC_LOAD_RIGHT))]
!   "!TARGET_MIPS16 && !TARGET_PATFREE"
    "<load>r\t%0,%2"
    [(set_attr "type" "load")
     (set_attr "mode" "<MODE>")])
*************** beq\t%2,%.,1b\;\
*** 2882,2888 ****
  	(unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
  		     (match_operand:QI 2 "memory_operand" "m")]
  		    UNSPEC_STORE_LEFT))]
!   "!TARGET_MIPS16"
    "<store>l\t%z1,%2"
    [(set_attr "type" "store")
     (set_attr "mode" "<MODE>")])
--- 2882,2888 ----
  	(unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
  		     (match_operand:QI 2 "memory_operand" "m")]
  		    UNSPEC_STORE_LEFT))]
!   "!TARGET_MIPS16 && !TARGET_PATFREE"
    "<store>l\t%z1,%2"
    [(set_attr "type" "store")
     (set_attr "mode" "<MODE>")])
*************** beq\t%2,%.,1b\;\
*** 2893,2899 ****
  		     (match_operand:QI 2 "memory_operand" "m")
  		     (match_dup 0)]
  		    UNSPEC_STORE_RIGHT))]
!   "!TARGET_MIPS16"
    "<store>r\t%z1,%2"
    [(set_attr "type" "store")
     (set_attr "mode" "<MODE>")])
--- 2893,2899 ----
  		     (match_operand:QI 2 "memory_operand" "m")
  		     (match_dup 0)]
  		    UNSPEC_STORE_RIGHT))]
!   "!TARGET_MIPS16 && !TARGET_PATFREE"
    "<store>r\t%z1,%2"
    [(set_attr "type" "store")
     (set_attr "mode" "<MODE>")])
Index: config/mips/mips.opt
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.opt,v
retrieving revision 1.4
diff -c -3 -p -r1.4 mips.opt
*** config/mips/mips.opt	6 May 2005 23:41:07 -0000	1.4
--- config/mips/mips.opt	13 May 2005 14:23:44 -0000
*************** mpaired-single
*** 181,186 ****
--- 181,190 ----
  Target Report Mask(PAIRED_SINGLE_FLOAT)
  Use paired-single floating-point instructions
  
+ mpatfree
+ Target Report Mask(PATFREE)
+ Do not use patented lwl/lwr/swl/swr instructions
+ 
  msingle-float
  Target Report RejectNegative Mask(SINGLE_FLOAT)
  Restrict the use of hardware floating-point instructions to 32-bit operations


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