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Re: [s390] macros patch 7/11
- From: Adrian Straetling <straetling at ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Ulrich dot Weigand at de dot ibm dot com
- Date: Mon, 9 May 2005 17:27:28 +0200
- Subject: Re: [s390] macros patch 7/11
- References: <20050509151411.GA11469@de.ibm.com>
Hi,
Here is the seventh patch dealing with shift operations.
2005-05-09 Adrian Straetling <straetling@de.ibm.com>
* config/s390/s390.md: ("SHIFT"): New mode macro.
("lr", "shift"): New mode attributes.
("ashldi3", "lshrdi3"): Merge.
("*ashldi3_31", "*lshrdi3"_31): Merge.
("*ashldi3_64", "*lshrdi3"_64): Merge.
("ashlsi3", "lshrsi3"): Merge.
Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig 2005-05-04 18:15:24.821486453 +0200
--- gcc/config/s390/s390.md 2005-05-04 18:15:27.551486453 +0200
***************
*** 259,264 ****
--- 259,276 ----
;; This macro allows to unify all exitstant 'set conditional' pattern.
(define_code_macro SCOND [ltu gtu leu geu])
+ ;; This macro allows some 'ashift' and 'lshiftrt' pattern to bed defined from
+ ;; the same template.
+ (define_code_macro SHIFT [ashift lshiftrt])
+
+
+ ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
+ ;; 'ashift' and "srdl" in 'lshiftrt'.
+ (define_code_attr lr [(ashift "l") (lshiftrt "r")])
+
+ ;; In SHIFT templates, this attribute holds the correct standard name for the
+ ;; pattern itself and the corresponding function calls.
+ (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
;; This attribute handles differences in the instruction 'type' and will result
;; in "RRE" for DImode and "RR" for SImode.
***************
*** 6329,6363 ****
;;
! ;;- Arithmetic shift instructions.
;;
;
! ; ashldi3 instruction pattern(s).
;
! (define_expand "ashldi3"
[(set (match_operand:DI 0 "register_operand" "")
! (ashift:DI (match_operand:DI 1 "register_operand" "")
! (match_operand:SI 2 "shift_count_operand" "")))]
""
"")
! (define_insn "*ashldi3_31"
[(set (match_operand:DI 0 "register_operand" "=d")
! (ashift:DI (match_operand:DI 1 "register_operand" "0")
! (match_operand:SI 2 "shift_count_operand" "Y")))]
"!TARGET_64BIT"
! "sldl\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
! (define_insn "*ashldi3_64"
[(set (match_operand:DI 0 "register_operand" "=d")
! (ashift:DI (match_operand:DI 1 "register_operand" "d")
! (match_operand:SI 2 "shift_count_operand" "Y")))]
"TARGET_64BIT"
! "sllg\t%0,%1,%Y2"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
--- 6341,6375 ----
;;
! ;;- Shift instructions.
;;
;
! ; (ashl|lshr)di3 instruction pattern(s).
;
! (define_expand "<shift>di3"
[(set (match_operand:DI 0 "register_operand" "")
! (SHIFT:DI (match_operand:DI 1 "register_operand" "")
! (match_operand:SI 2 "shift_count_operand" "")))]
""
"")
! (define_insn "*<shift>di3_31"
[(set (match_operand:DI 0 "register_operand" "=d")
! (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
! (match_operand:SI 2 "shift_count_operand" "Y")))]
"!TARGET_64BIT"
! "s<lr>dl\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
! (define_insn "*<shift>di3_64"
[(set (match_operand:DI 0 "register_operand" "=d")
! (SHIFT:DI (match_operand:DI 1 "register_operand" "d")
! (match_operand:SI 2 "shift_count_operand" "Y")))]
"TARGET_64BIT"
! "s<lr>lg\t%0,%1,%Y2"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
***************
*** 6442,6456 ****
;
! ; ashlsi3 instruction pattern(s).
;
! (define_insn "ashlsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
! (ashift:SI (match_operand:SI 1 "register_operand" "0")
! (match_operand:SI 2 "shift_count_operand" "Y")))]
""
! "sll\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
--- 6454,6468 ----
;
! ; (ashl|lshr)si3 instruction pattern(s).
;
! (define_insn "<shift>si3"
[(set (match_operand:SI 0 "register_operand" "=d")
! (SHIFT:SI (match_operand:SI 1 "register_operand" "0")
! (match_operand:SI 2 "shift_count_operand" "Y")))]
""
! "s<lr>l\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
***************
*** 6494,6546 ****
;;
- ;;- logical shift instructions.
- ;;
-
- ;
- ; lshrdi3 instruction pattern(s).
- ;
-
- (define_expand "lshrdi3"
- [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "shift_count_operand" "")))]
- ""
- "")
-
- (define_insn "*lshrdi3_31"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:SI 2 "shift_count_operand" "Y")))]
- "!TARGET_64BIT"
- "srdl\t%0,%Y2"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "reg")])
-
- (define_insn "*lshrdi3_64"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "shift_count_operand" "Y")))]
- "TARGET_64BIT"
- "srlg\t%0,%1,%Y2"
- [(set_attr "op_type" "RSE")
- (set_attr "atype" "reg")])
-
- ;
- ; lshrsi3 instruction pattern(s).
- ;
-
- (define_insn "lshrsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:SI 2 "shift_count_operand" "Y")))]
- ""
- "srl\t%0,%Y2"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "reg")])
-
-
- ;;
;; Branch instruction patterns.
;;
--- 6506,6511 ----