Patch for 3.4.4 , fix for bugs #19750 and #20036

[Dinar Temirbulatov <dtemirbulatov at ru dot mvista dot com>]

Hi, this patch fixes bugs #19750 and #20036, also vector-[12]_x.c and 
i386-sse-2.c testcases for the x86_64 architecture.

[dinar@dinar gcc.dg]$ 
/home/dinar/work/gnu/tools/x86_64-unknown-linux-gnu/gcc-3.4.4-glibc-2.3.3/bin/x86_64-unknown-linux-gnu-gcc 
-v
Reading specs from 
/home/dinar/work/gnu/tools/x86_64-unknown-linux-gnu/gcc-3.4.4-glibc-2.3.3/lib/gcc/x86_64-unknown-linux-gnu/3.4.4/specs
Configured with: 
/home/dinar/work/gnu/crosstool-0.29/build/x86_64-unknown-linux-gnu/gcc-3.4.4-glibc-2.3.3/gcc-3.4.4/configure 
--target=x86_64-unknown-linux-gnu --host=i686-host_pc-linux-gnu 
--prefix=/home/dinar/work/gnu/tools/x86_64-unknown-linux-gnu/gcc-3.4.4-glibc-2.3.3 
--disable-multilib 
--with-sysroot=/home/dinar/work/gnu/tools/x86_64-unknown-linux-gnu/gcc-3.4.4-glibc-2.3.3/x86_64-unknown-linux-gnu/sys-root 
--with-local-prefix=/home/dinar/work/gnu/tools/x86_64-unknown-linux-gnu/gcc-3.4.4-glibc-2.3.3/x86_64-unknown-linux-gnu/sys-root 
--disable-nls --enable-threads=posix --enable-symvers=gnu 
--enable-__cxa_atexit --enable-languages=c,c++ --enable-shared 
--enable-c99 --enable-long-long
Thread model: posix
gcc version 3.4.4 20050505 (prerelease)

thanks, Dinar.
diff -ruN gcc-orig/gcc/config/i386/i386.c gcc/gcc/config/i386/i386.c
--- gcc-orig/gcc/config/i386/i386.c	2005-05-06 15:10:49.000000000 +0400
+++ gcc/gcc/config/i386/i386.c	2005-05-06 15:38:23.000000000 +0400
@@ -2228,6 +2228,8 @@
     case CSImode:
     case CHImode:
     case CQImode:
+    case V1DImode:
+    case V2HImode:
       if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
 	classes[0] = X86_64_INTEGERSI_CLASS;
       else
@@ -2284,6 +2286,8 @@
     case V4HImode:
     case V8QImode:
       return 0;
+    case V16SFmode:
+      return 0;
     case BLKmode:
     case VOIDmode:
       return 0;
@@ -3239,7 +3243,7 @@
 
 
       need_temp = ((needed_intregs && TYPE_ALIGN (type) > 64)
-		   || TYPE_ALIGN (type) > 128);
+		   || TYPE_ALIGN (type) > 128) && !REG_P (container);
 
       /* In case we are passing structure, verify that it is consecutive block
          on the register save area.  If not we need to do moves.  */
@@ -14601,10 +14605,12 @@
 
     case IX86_BUILTIN_CLFLUSH:
 	arg0 = TREE_VALUE (arglist);
-	op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
-	icode = CODE_FOR_sse2_clflush;
-	if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
-	    op0 = copy_to_mode_reg (Pmode, op0);
+	{
+	  rtx addr = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
+          if (! address_operand (addr, Pmode))
+	    addr = copy_to_mode_reg (Pmode, addr);
+	  op0 = gen_rtx_MEM (QImode, addr);
+	}
 
 	emit_insn (gen_sse2_clflush (op0));
 	return 0;
diff -ruN gcc-orig/gcc/config/i386/i386.md gcc/gcc/config/i386/i386.md
--- gcc-orig/gcc/config/i386/i386.md	2005-05-06 15:10:49.000000000 +0400
+++ gcc/gcc/config/i386/i386.md	2005-05-06 15:38:23.000000000 +0400
@@ -22664,7 +22664,22 @@
 
 ;; SSE2 moves
 
-(define_insn "sse2_movapd"
+(define_expand "sse2_movapd"
+  [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
+	(unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "")]
+		     UNSPEC_MOVA))]
+  "TARGET_SSE2"
+{
+  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+    {
+      rtx tmp = gen_reg_rtx (V2DFmode);
+      emit_insn (gen_sse2_movapd (tmp, operands[1]));
+      emit_move_insn (operands[0], tmp);
+      DONE;
+    }
+})
+
+(define_insn "*sse2_movapd_1"
   [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
 	(unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
 		     UNSPEC_MOVA))]
@@ -22674,7 +22689,22 @@
   [(set_attr "type" "ssemov")
    (set_attr "mode" "V2DF")])
 
-(define_insn "sse2_movupd"
+(define_expand "sse2_movupd"
+  [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
+	(unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "")]
+		     UNSPEC_MOVU))]
+  "TARGET_SSE2"
+{
+  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+    {
+      rtx tmp = gen_reg_rtx (V2DFmode);
+      emit_insn (gen_sse2_movupd (tmp, operands[1]));
+      emit_move_insn (operands[0], tmp);
+      DONE;
+    }
+})
+
+(define_insn "*sse2_movupd_1"
   [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
 	(unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
 		     UNSPEC_MOVU))]
@@ -22817,7 +22847,30 @@
   [(set_attr "type" "ssecvt")
    (set_attr "mode" "DF")])
 
-(define_insn "sse2_movsd"
+(define_expand "sse2_movsd"
+  [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
+	(vec_merge:V2DF
+	 (match_operand:V2DF 1 "nonimmediate_operand" "")
+	 (match_operand:V2DF 2 "nonimmediate_operand" "")
+	 (const_int 1)))]
+  "TARGET_SSE2"
+{
+  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[2]) == MEM)
+    {
+      rtx tmp = gen_reg_rtx (V2DFmode);
+      emit_move_insn (tmp, operands[1]);
+      emit_insn (gen_sse2_movsd (tmp, tmp, operands[2]));
+      emit_move_insn (operands[0], tmp);
+      DONE;
+    }
+  else if (! rtx_equal_p (operands[0], operands[1]))
+    {
+      emit_move_insn (operands[0], operands [1]);
+      operands [1] = operands [0];
+    }
+})
+
+(define_insn "*sse2_movsd_1"
   [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
 	(vec_merge:V2DF
 	 (match_operand:V2DF 1 "nonimmediate_operand" "0,0,0")
@@ -22853,7 +22906,7 @@
    (set_attr "mode" "V2DF")])
 
 (define_insn "sse2_clflush"
-  [(unspec_volatile [(match_operand 0 "address_operand" "p")]
+  [(unspec_volatile [(match_operand 0 "memory_operand" "m")]
 		    UNSPECV_CLFLUSH)]
   "TARGET_SSE2"
   "clflush %0"