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Re: [PATCH] AVR: implement HI/SI logic operations and sign/zero extension by define_insn_and_split instead of define_insn
Björn Haase <bjoern.m.haase@web.de> writes:
> Am Donnerstag, 14. April 2005 18:03 schrieb Denis Chertykov:
> > "*{
> > if (which_alternative==0)
> > return (AS2 (or,%A0,%A2) CR_TAB
> > AS2 (or,%B0,%B2));
> > ...
> > ...
> > }")
> >
> > Must be changed to:
> >
> > ""
> > "#"
> > ...
> > ...)
> >
>
> Understood. I have thought about doing it this way (removing the template
> completely). I simply did not dare to do it, because I did not know for sure
> whether the standard output pattern might still be used for selected
> optimizer options or when switching on some selected debugging
> level.
Do not worry. Look at rs6000 port for example.
>
> >
> > 2. The following code in your patterns seems strange:
> > "if (GET_CODE(operands[2]) == CONST_INT)
> > {
> > /* If operands[2] is a register, use the template above. */
> > int value = INTVAL(operands[2]);
> > int j;
> > int bytes_of_mode = 2;
> > for (j=0; j < bytes_of_mode; j++)
> > ...
> > ..."
> >
> > Look at ARM port:
> >
> > ;; Boolean and,ior,xor insns
> >
> > ;; Split up double word logical operations
> >
> > ;; Split up simple DImode logical operations. Simply perform the logical
> > ;; operation on the upper and lower halves of the registers.
> > (define_split
> > [(set (match_operand:DI 0 "s_register_operand" "")
> > (match_operator:DI 6 "logical_binary_operator"
> > [(match_operand:DI 1 "s_register_operand" "")
> > (match_operand:DI 2 "s_register_operand" "")]))]
> > "TARGET_ARM && reload_completed && ! IS_IWMMXT_REGNUM (REGNO
> > (operands[0]))" [(set (match_dup 0) (match_op_dup:SI 6 [(match_dup 1)
> > (match_dup 2)])) (set (match_dup 3) (match_op_dup:SI 6 [(match_dup 4)
> > (match_dup 5)]))] "
> > {
> > operands[3] = gen_highpart (SImode, operands[0]);
> > operands[0] = gen_lowpart (SImode, operands[0]);
> > operands[4] = gen_highpart (SImode, operands[1]);
> > operands[1] = gen_lowpart (SImode, operands[1]);
> > operands[5] = gen_highpart (SImode, operands[2]);
> > operands[2] = gen_lowpart (SImode, operands[2]);
> > }"
> > )
> >
> > gen_lowpart and gen_highpart will work right with constant operand.
> >
> > Denis.
> The reason why I have written a separate treatment for constant operands is,
> that
>
> 1.) It is necessary to replace andi rXX,0 and ori rYY,0xFF by ldi rXX,0 and
> ldi rYY,0xFF in order to make sure that GCC finds out that it could optimize
> a two instruction sequence like "ldi rXX,23 ; andi rXX,0" to "ldi rXX,0". If
> one emits RTX for "set (reg:QI ZZ) (and:QI (reg:QI XX) (const_int 0))"
> instead of the similar "set (reg:QI ZZ) (const_int 0)" , gcc would keep
> preceding instructions that write rXX, like ldi rXX,23.
IMHO GCC must have such optimization without your code.
>
> 2.) A spurious ori rXX,0 or andi rYY,0xFF would not always be
> optimized away.
It this true ? Are you sure ?
> I think removal of all logic combinations without side effect except for the
> condition code is useful. The only problem that could occure is a sign test
> immediately after the operation. However, for the occasion that one would
> like to have a sign test immediately after the logic operation, there still
> is the fairly efficient "sbrs rXX,7; rjmp _label" pattern (one additional
> instruction in the worst case).
>
> It seems that having to do these optimization explicitly is the price that we
> are paying for splitting after reload. The optimization passes before reload
> probably would be able to do such optimizations by themselves.
I'm agree.
Denis.