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[PATCH] ARM clean up tuning attributes
- From: Richard Earnshaw <rearnsha at gcc dot gnu dot org>
- To: gcc-patches <gcc-patches at gcc dot gnu dot org>
- Date: Sat, 09 Apr 2005 13:10:00 +0100
- Subject: [PATCH] ARM clean up tuning attributes
- Organization: GNU
This patch cleans up some of the CPU tuning attributes. Mostly it's
just name changes, but there's one technical change in that we now model
the write buffer only on those CPUs that have one (previously we did
this for all arm6 & 7 cores even if they didn't have one in practice).
Tested on an arm-elf cross.
2005-04-09 Richard Earnshaw <richard.earnshaw@arm.com>
* arm.c (FL_WBUF): Define.
(arm_tune_strongarm): Renamed from arm_is_strong. All uses changed.
(arm_is_6_or_7): Delete.
(arm_tune_wbuf): New.
(arm_override_options): Set arm_tune_wbuf.
* arm.h (arm_tune_strongarm): Renamed from arm_is_strong.
(arm_is_6_or_7): Delete declaration.
(arm_tune_wbuf): New declartion.
* arm.md (is_strongarm): Derive from arm_tune_strongarm.
(model_wbuf): Derive from arm_tune_wbuf.
* arm-cores.def (arm600, arm610, arm620, arm700, arm700i, arm710)
(arm720, arm710c, arm7100, arm7500, arm7500fe, arm710t, arm720t)
(arm740t): Mark CPUs as having a write buffer.
R.
Index: arm-cores.def
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm-cores.def,v
retrieving revision 1.11
diff -p -r1.11 arm-cores.def
*** arm-cores.def 14 Dec 2004 14:06:02 -0000 1.11
--- arm-cores.def 9 Apr 2005 11:53:22 -0000
*************** ARM_CORE("arm3", arm3, 2, FL_CO_PROC |
*** 43,64 ****
/* V3 Architecture Processors */
ARM_CORE("arm6", arm6, 3, FL_CO_PROC | FL_MODE26, slowmul)
ARM_CORE("arm60", arm60, 3, FL_CO_PROC | FL_MODE26, slowmul)
! ARM_CORE("arm600", arm600, 3, FL_CO_PROC | FL_MODE26, slowmul)
! ARM_CORE("arm610", arm610, 3, FL_MODE26, slowmul)
! ARM_CORE("arm620", arm620, 3, FL_CO_PROC | FL_MODE26, slowmul)
ARM_CORE("arm7", arm7, 3, FL_CO_PROC | FL_MODE26, slowmul)
ARM_CORE("arm7d", arm7d, 3, FL_CO_PROC | FL_MODE26, slowmul)
ARM_CORE("arm7di", arm7di, 3, FL_CO_PROC | FL_MODE26, slowmul)
ARM_CORE("arm70", arm70, 3, FL_CO_PROC | FL_MODE26, slowmul)
! ARM_CORE("arm700", arm700, 3, FL_CO_PROC | FL_MODE26, slowmul)
! ARM_CORE("arm700i", arm700i, 3, FL_CO_PROC | FL_MODE26, slowmul)
! ARM_CORE("arm710", arm710, 3, FL_MODE26, slowmul)
! ARM_CORE("arm720", arm720, 3, FL_MODE26, slowmul)
! ARM_CORE("arm710c", arm710c, 3, FL_MODE26, slowmul)
! ARM_CORE("arm7100", arm7100, 3, FL_MODE26, slowmul)
! ARM_CORE("arm7500", arm7500, 3, FL_MODE26, slowmul)
/* Doesn't have an external co-proc, but does have embedded fpa. */
! ARM_CORE("arm7500fe", arm7500fe, 3, FL_CO_PROC | FL_MODE26, slowmul)
/* V3M Architecture Processors */
/* arm7m doesn't exist on its own, but only with D, ("and", and I), but
--- 43,64 ----
/* V3 Architecture Processors */
ARM_CORE("arm6", arm6, 3, FL_CO_PROC | FL_MODE26, slowmul)
ARM_CORE("arm60", arm60, 3, FL_CO_PROC | FL_MODE26, slowmul)
! ARM_CORE("arm600", arm600, 3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
! ARM_CORE("arm610", arm610, 3, FL_MODE26 | FL_WBUF, slowmul)
! ARM_CORE("arm620", arm620, 3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
ARM_CORE("arm7", arm7, 3, FL_CO_PROC | FL_MODE26, slowmul)
ARM_CORE("arm7d", arm7d, 3, FL_CO_PROC | FL_MODE26, slowmul)
ARM_CORE("arm7di", arm7di, 3, FL_CO_PROC | FL_MODE26, slowmul)
ARM_CORE("arm70", arm70, 3, FL_CO_PROC | FL_MODE26, slowmul)
! ARM_CORE("arm700", arm700, 3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
! ARM_CORE("arm700i", arm700i, 3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
! ARM_CORE("arm710", arm710, 3, FL_MODE26 | FL_WBUF, slowmul)
! ARM_CORE("arm720", arm720, 3, FL_MODE26 | FL_WBUF, slowmul)
! ARM_CORE("arm710c", arm710c, 3, FL_MODE26 | FL_WBUF, slowmul)
! ARM_CORE("arm7100", arm7100, 3, FL_MODE26 | FL_WBUF, slowmul)
! ARM_CORE("arm7500", arm7500, 3, FL_MODE26 | FL_WBUF, slowmul)
/* Doesn't have an external co-proc, but does have embedded fpa. */
! ARM_CORE("arm7500fe", arm7500fe, 3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
/* V3M Architecture Processors */
/* arm7m doesn't exist on its own, but only with D, ("and", and I), but
*************** ARM_CORE("strongarm1100", strongarm1100,
*** 76,86 ****
ARM_CORE("strongarm1110", strongarm1110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul)
/* V4T Architecture Processors */
! ARM_CORE("arm7tdmi", arm7tdmi, 4T, FL_CO_PROC , fastmul)
! ARM_CORE("arm7tdmi-s", arm7tdmis, 4T, FL_CO_PROC , fastmul)
! ARM_CORE("arm710t", arm710t, 4T, 0 , fastmul)
! ARM_CORE("arm720t", arm720t, 4T, 0 , fastmul)
! ARM_CORE("arm740t", arm740t, 4T, 0 , fastmul)
ARM_CORE("arm9", arm9, 4T, FL_LDSCHED, fastmul)
ARM_CORE("arm9tdmi", arm9tdmi, 4T, FL_LDSCHED, fastmul)
ARM_CORE("arm920", arm920, 4T, FL_LDSCHED, fastmul)
--- 76,86 ----
ARM_CORE("strongarm1110", strongarm1110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul)
/* V4T Architecture Processors */
! ARM_CORE("arm7tdmi", arm7tdmi, 4T, FL_CO_PROC , fastmul)
! ARM_CORE("arm7tdmi-s", arm7tdmis, 4T, FL_CO_PROC , fastmul)
! ARM_CORE("arm710t", arm710t, 4T, FL_WBUF, fastmul)
! ARM_CORE("arm720t", arm720t, 4T, FL_WBUF, fastmul)
! ARM_CORE("arm740t", arm740t, 4T, FL_WBUF, fastmul)
ARM_CORE("arm9", arm9, 4T, FL_LDSCHED, fastmul)
ARM_CORE("arm9tdmi", arm9tdmi, 4T, FL_LDSCHED, fastmul)
ARM_CORE("arm920", arm920, 4T, FL_LDSCHED, fastmul)
Index: arm.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.c,v
retrieving revision 1.438
diff -p -r1.438 arm.c
*** arm.c 8 Apr 2005 13:34:19 -0000 1.438
--- arm.c 9 Apr 2005 11:53:24 -0000
*************** static int thumb_call_reg_needed;
*** 386,391 ****
--- 386,393 ----
#define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
media instructions. */
#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
+ #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
+ Note: ARM6 & 7 derivatives only. */
#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
*************** int arm_arch6 = 0;
*** 438,444 ****
int arm_ld_sched = 0;
/* Nonzero if this chip is a StrongARM. */
! int arm_is_strong = 0;
/* Nonzero if this chip is a Cirrus variant. */
int arm_arch_cirrus = 0;
--- 440,446 ----
int arm_ld_sched = 0;
/* Nonzero if this chip is a StrongARM. */
! int arm_tune_strongarm = 0;
/* Nonzero if this chip is a Cirrus variant. */
int arm_arch_cirrus = 0;
*************** int arm_arch_xscale = 0;
*** 452,459 ****
/* Nonzero if tuning for XScale */
int arm_tune_xscale = 0;
! /* Nonzero if this chip is an ARM6 or an ARM7. */
! int arm_is_6_or_7 = 0;
/* Nonzero if generating Thumb instructions. */
int thumb_code = 0;
--- 454,462 ----
/* Nonzero if tuning for XScale */
int arm_tune_xscale = 0;
! /* Nonzero if we want to tune for stores that access the write-buffer.
! This typicallly means an ARM6 or ARM7 with MMU or MPU. */
! int arm_tune_wbuf = 0;
/* Nonzero if generating Thumb instructions. */
int thumb_code = 0;
*************** arm_override_options (void)
*** 980,989 ****
arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
! arm_is_strong = (tune_flags & FL_STRONG) != 0;
thumb_code = (TARGET_ARM == 0);
! arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
! && !(tune_flags & FL_ARCH4))) != 0;
arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
--- 983,991 ----
arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
! arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
thumb_code = (TARGET_ARM == 0);
! arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
*************** arm_override_options (void)
*** 1182,1188 ****
/* StrongARM has early execution of branches, so a sequence
that is worth skipping is shorter. */
! if (arm_is_strong)
max_insns_skipped = 3;
}
--- 1184,1190 ----
/* StrongARM has early execution of branches, so a sequence
that is worth skipping is shorter. */
! if (arm_tune_strongarm)
max_insns_skipped = 3;
}
*************** use_return_insn (int iscond, rtx sibling
*** 1396,1402 ****
/* On StrongARM, conditional returns are expensive if they aren't
taken and multiple registers have been stacked. */
! if (iscond && arm_is_strong)
{
/* Conditional return when just the LR is stored is a simple
conditional-load instruction, that's not expensive. */
--- 1398,1404 ----
/* On StrongARM, conditional returns are expensive if they aren't
taken and multiple registers have been stacked. */
! if (iscond && arm_tune_strongarm)
{
/* Conditional return when just the LR is stored is a simple
conditional-load instruction, that's not expensive. */
Index: arm.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.h,v
retrieving revision 1.271
diff -p -r1.271 arm.h
*** arm.h 7 Apr 2005 11:24:11 -0000 1.271
--- arm.h 9 Apr 2005 11:53:24 -0000
*************** extern int arm_ld_sched;
*** 525,531 ****
extern int thumb_code;
/* Nonzero if this chip is a StrongARM. */
! extern int arm_is_strong;
/* Nonzero if this chip is a Cirrus variant. */
extern int arm_arch_cirrus;
--- 525,531 ----
extern int thumb_code;
/* Nonzero if this chip is a StrongARM. */
! extern int arm_tune_strongarm;
/* Nonzero if this chip is a Cirrus variant. */
extern int arm_arch_cirrus;
*************** extern int arm_arch_iwmmxt;
*** 536,546 ****
/* Nonzero if this chip is an XScale. */
extern int arm_arch_xscale;
! /* Nonzero if tuning for XScale */
extern int arm_tune_xscale;
! /* Nonzero if this chip is an ARM6 or an ARM7. */
! extern int arm_is_6_or_7;
/* Nonzero if we should define __THUMB_INTERWORK__ in the
preprocessor.
--- 536,546 ----
/* Nonzero if this chip is an XScale. */
extern int arm_arch_xscale;
! /* Nonzero if tuning for XScale. */
extern int arm_tune_xscale;
! /* Nonzero if tuning for stores via the write buffer. */
! extern int arm_tune_wbuf;
/* Nonzero if we should define __THUMB_INTERWORK__ in the
preprocessor.
Index: arm.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.md,v
retrieving revision 1.196
diff -p -r1.196 arm.md
*** arm.md 8 Apr 2005 13:34:24 -0000 1.196
--- arm.md 9 Apr 2005 11:53:24 -0000
***************
*** 135,141 ****
; IS_STRONGARM is set to 'yes' when compiling for StrongARM, it affects
; scheduling decisions for the load unit and the multiplier.
! (define_attr "is_strongarm" "no,yes" (const (symbol_ref "arm_is_strong")))
; IS_XSCALE is set to 'yes' when compiling for XScale.
(define_attr "is_xscale" "no,yes" (const (symbol_ref "arm_tune_xscale")))
--- 135,141 ----
; IS_STRONGARM is set to 'yes' when compiling for StrongARM, it affects
; scheduling decisions for the load unit and the multiplier.
! (define_attr "is_strongarm" "no,yes" (const (symbol_ref "arm_tune_strongarm")))
; IS_XSCALE is set to 'yes' when compiling for XScale.
(define_attr "is_xscale" "no,yes" (const (symbol_ref "arm_tune_xscale")))
***************
*** 267,273 ****
; have one. Later ones, such as StrongARM, have write-back caches, so don't
; suffer blockages enough to warrant modelling this (and it can adversely
; affect the schedule).
! (define_attr "model_wbuf" "no,yes" (const (symbol_ref "arm_is_6_or_7")))
; WRITE_CONFLICT implies that a read following an unrelated write is likely
; to stall the processor. Used with model_wbuf above.
--- 267,273 ----
; have one. Later ones, such as StrongARM, have write-back caches, so don't
; suffer blockages enough to warrant modelling this (and it can adversely
; affect the schedule).
! (define_attr "model_wbuf" "no,yes" (const (symbol_ref "arm_tune_wbuf")))
; WRITE_CONFLICT implies that a read following an unrelated write is likely
; to stall the processor. Used with model_wbuf above.