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Re: [PATCH, i386] Avoid FP constants in wrong register set

Richard Henderson wrote:

On Tue, Jan 25, 2005 at 10:43:25AM +0100, Uros Bizjak wrote:

@@ -3755,6 +3760,10 @@ standard_80387_constant_rtx (int idx)
standard_sse_constant_p (rtx x)
+ /* Do not put x87 constants into SSE register for !TARGET_SSE_MATH. */
+ return 0;

I would expect this to start loading 0 from memory instead of using xorps when talking about xmmintrin.h stuff.

Hm, aren't these always vector mode (V4SF etc.) zeros? SSE_FLOAT_MODE_P shouldn't trigger for this.

However, patched standard_{sse,x87}_constant_p functions now break because of this change to ix86_preferred_reload_class():

 /* All classes can load zeros.  */
 if (x == CONST0_RTX (GET_MODE (x)))
   return class;

In this case, reg allocator sometimes can't decide whether x87 or SSE register should be used to load zero. If standard_{sse,x87} constant_p functions are patched to reject wrong {DF,SF}mode registers, -mfpmath=sse breaks because allocator already choosed wrong preferred register set:

pattern.cpp:2537: error: insn does not satisfy its constraints:
(insn 367 187 280 8 (set (reg/v:DF 8 st [orig:76 cf ] [76])
(const_double:DF 0 [0x0] 0.0 [0x0.0p+0])) 64 {*movdf_nointeger} (nil)

I suggest that for TARGET_SSE_MATH, SSE registers are preferred for {DF,SF}mode constants (including zero) and vice versa for -mfpmath=387. Otherwise, these situations can occur:

80fe5bc: d9 ee fldz 80fe5be: dd 5c 24 40 fstpl 0x40(%esp,1)
80fe5c2: f2 0f 10 5c 24 40 movsd 0x40(%esp,1),%xmm3


804c4d7: d9 e8 fld1 804c4d9: dd 5c 24 28 fstpl 0x28(%esp,1)
804c4dd: f2 0f 10 64 24 28 movsd 0x28(%esp,1),%xmm4

If constants would be _forced_ into XMM register, further calculations wouldn't load constant from memory, because it will be already in the XMM register.


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