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[committed] Clear MIPS IV Flush to Zero bit on IRIX

For some reason, n32 and n64 IRIX applications are usually run with the
MIPS IV Flush to Zero bit set, meaning that MIPS IV systems will not
handle subnormals correctly by default.  Googling suggests that some
people see this as a bug in the OS, and it's certainly odd to have a
default that causes MIPS III and MIPS IV systems behave differently.

Anyway, gcc-generated code should really handle subnormals correctly by
default, without any special action from the user.  This patch tries to
ensure this by clearing the bit at application start-up time.

I couldn't decide whether it was appropriate to do this for shared
libraries as well as executables, so for the time being, the new
code is only linked in if !shared.  This also means that shared library
INIT code will still run with the bit set, so I might change this later.
Let me know if you have any thoughts one way or the other.

I also wondered about adding a new command-line option to enable or
disable the feature, but I didn't want Yet Another Target Switch
unless there was a real need.  (But maybe my reluctance to do this
for shared libraries shows that there _is_ a real need...)

Patch bootstrapped & regression tested on mips-sgi-irix6.5.  It fixes
the ieee/mul-subnormal-single-1.c failures.  New results available here:

Applied to mainline.


	* config/mips/irix-csr.c: New file.
	* config/mips/t-iris6 (irix-csr.o): New rule to build it.
	(EXTRA_MULTILIB_PARTS): Add irix-csr.o.
	* config/mips/iris6.h (ENDFILE_SPEC): Include it in n32 and n64

Index: config/mips/iris6.h
RCS file: /cvs/gcc/gcc/gcc/config/mips/iris6.h,v
retrieving revision 1.79
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.79 iris6.h
--- config/mips/iris6.h	20 Aug 2004 10:20:09 -0000	1.79
+++ config/mips/iris6.h	24 Jan 2005 21:25:02 -0000
@@ -97,7 +97,8 @@ #define LIBGCC_SPEC \
 #define ENDFILE_SPEC \
-  "crtend.o%s irix-crtn.o%s \
+  "%{!shared:%{mabi=n32|mabi=64:irix-csr.o%s}} \
+   crtend.o%s irix-crtn.o%s \
    %{!shared: \
Index: config/mips/t-iris6
RCS file: /cvs/gcc/gcc/gcc/config/mips/t-iris6,v
retrieving revision 1.26
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.26 t-iris6
--- config/mips/t-iris6	8 Jan 2005 11:59:25 -0000	1.26
+++ config/mips/t-iris6	24 Jan 2005 21:25:02 -0000
@@ -19,3 +19,9 @@ tp-bit.c: $(srcdir)/config/fp-bit.c
 	echo '# define TFLOAT' >> tp-bit.c
 	cat $(srcdir)/config/fp-bit.c >> tp-bit.c
 	echo '#endif' >> tp-bit.c
+$(T)irix-csr.o: $(srcdir)/config/mips/irix-csr.c $(GCC_PASSES)
+	  -c -o $@ $<
diff -u /dev/null config/mips/irix-csr.c
--- /dev/null	Fri Apr 23 00:21:55 2004
+++ config/mips/irix-csr.c	Mon Jan 24 21:24:47 2005
@@ -0,0 +1,17 @@
+#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
+#include <sys/fpu.h>
+/* n32 and n64 applications usually run with the MIPS IV Flush to Zero
+   bit set.  Clear it here so that gcc-generated code will handle
+   subnormals correctly by default.  */
+static void __attribute__((constructor))
+clear_flush_to_zero (void)
+  union fpc_csr csr;
+  csr.fc_word = get_fpc_csr ();
+  csr.fc_struct.flush = 0;
+  set_fpc_csr (csr.fc_word);

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